1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence Quad SPI controller
10 - Vaishnav Achath <vaishnav.a@ti.com>
13 - $ref: spi-controller.yaml#
18 const: xlnx,versal-ospi-1.0
26 const: starfive,jh7110-qspi
37 enum: [ qspi, qspi-ocp, rstc_ref ]
48 enum: [ qspi, qspi-ocp ]
53 const: amd,pensando-elba-qspi
57 enum: [ 128, 256, 1024 ]
70 - amd,pensando-elba-qspi
74 - xlnx,versal-ospi-1.0
76 - starfive,jh7110-qspi
77 - const: cdns,qspi-nor
78 - const: cdns,qspi-nor
82 - description: the controller register set
83 - description: the controller data area
103 Size of the data FIFO in words.
104 $ref: /schemas/types.yaml#/definitions/uint32
107 $ref: /schemas/types.yaml#/definitions/uint32
109 Bus width of the data FIFO in bytes.
112 cdns,trigger-address:
113 $ref: /schemas/types.yaml#/definitions/uint32
115 32-bit indirect AHB trigger address.
120 Flag to indicate whether decoder is used to select different chip select
121 for different memory regions.
126 Flag to indicate that QSPI return clock is used to latch the read
127 data rather than the QSPI clock. Make sure that QSPI return clock
128 is populated on the board before using this property.
141 enum: [ qspi, qspi-ocp, rstc_ref ]
150 - cdns,trigger-address
154 unevaluatedProperties: false
159 compatible = "cdns,qspi-nor";
160 #address-cells = <1>;
162 reg = <0xff705000 0x1000>,
164 interrupts = <0 151 4>;
165 clocks = <&qspi_clk>;
166 cdns,fifo-depth = <128>;
167 cdns,fifo-width = <4>;
168 cdns,trigger-address = <0x00000000>;
169 resets = <&rst 0x1>, <&rst 0x2>;
170 reset-names = "qspi", "qspi-ocp";
173 compatible = "jedec,spi-nor";