1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for the Cadence QSPI controller.
10 See spi-peripheral-props.yaml for more info.
13 - Vaishnav Achath <vaishnav.a@ti.com>
18 $ref: /schemas/types.yaml#/definitions/uint32
20 Delay for read capture logic, in clock cycles.
24 Delay in nanoseconds for the length that the master mode chip select
25 outputs are de-asserted between transactions.
29 Delay in nanoseconds between one chip select being de-activated
30 and the activation of another.
34 Delay in nanoseconds between last bit of current transaction and
35 deasserting the device chip select (qspi_n_ss_out).
39 Delay in nanoseconds between setting qspi_n_ss_out low and
42 additionalProperties: true