kconfig: simplify symbol-search code
[carl9170fw.git] / carlfw / src / rf.c
1 /*
2  * carl9170 firmware - used by the ar9170 wireless device
3  *
4  * PHY and RF functions
5  *
6  * Copyright (c) 2000-2005 ZyDAS Technology Corporation
7  * Copyright (c) 2007-2009 Atheros Communications, Inc.
8  * Copyright    2009    Johannes Berg <johannes@sipsolutions.net>
9  * Copyright 2009-2011  Christian Lamparter <chunkeey@googlemail.com>
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License, or
14  * (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License along
22  * with this program; if not, write to the Free Software Foundation, Inc.,
23  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
24  */
25
26 #include "carl9170.h"
27 #include "timer.h"
28 #include "printf.h"
29 #include "rf.h"
30 #include "shared/phy.h"
31
32 #ifdef CONFIG_CARL9170FW_RADIO_FUNCTIONS
33 static void set_channel_end(void)
34 {
35         /* Manipulate CCA threshold to resume transmission */
36         set(AR9170_PHY_REG_CCA_THRESHOLD, 0x0);
37         /* Disable Virtual CCA */
38         andl(AR9170_MAC_REG_QOS_PRIORITY_VIRTUAL_CCA,
39              ~AR9170_MAC_VIRTUAL_CCA_ALL);
40
41         fw.phy.state = CARL9170_PHY_ON;
42 }
43
44 void rf_notify_set_channel(void)
45 {
46         /* Manipulate CCA threshold to stop transmission */
47         set(AR9170_PHY_REG_CCA_THRESHOLD, 0x300);
48         /* Enable Virtual CCA */
49         orl(AR9170_MAC_REG_QOS_PRIORITY_VIRTUAL_CCA,
50             AR9170_MAC_VIRTUAL_CCA_ALL);
51
52         /* reset CCA stats */
53         fw.tally.active = 0;
54         fw.tally.cca = 0;
55         fw.tally.tx_time = 0;
56         fw.phy.state = CARL9170_PHY_OFF;
57 }
58
59 /*
60  * Update delta slope coeff man and exp
61  */
62 static void hw_turn_off_dyn(const uint32_t delta_slope_coeff_exp,
63                             const uint32_t delta_slope_coeff_man,
64                             const uint32_t delta_slope_coeff_exp_shgi,
65                             const uint32_t delta_slope_coeff_man_shgi)
66 {
67         uint32_t tmp;
68
69         tmp = get_async(AR9170_PHY_REG_TIMING3) & 0x00001fff;
70         tmp |= (delta_slope_coeff_man << AR9170_PHY_TIMING3_DSC_MAN_S) &
71                 AR9170_PHY_TIMING3_DSC_MAN;
72         tmp |= (delta_slope_coeff_exp << AR9170_PHY_TIMING3_DSC_EXP_S) &
73                 AR9170_PHY_TIMING3_DSC_EXP;
74
75         set(AR9170_PHY_REG_TIMING3, tmp);
76
77         tmp = (delta_slope_coeff_man_shgi << AR9170_PHY_HALFGI_DSC_MAN_S) &
78                 AR9170_PHY_HALFGI_DSC_MAN;
79
80         tmp |= (delta_slope_coeff_exp_shgi << AR9170_PHY_HALFGI_DSC_EXP_S) &
81                 AR9170_PHY_HALFGI_DSC_EXP;
82
83         set(AR9170_PHY_REG_HALFGI, tmp);
84 }
85
86 static void program_ADDAC(void)
87 {
88         /* ??? Select Internal ADDAC ??? (is external radio) */
89         set(AR9170_PHY_REG_ADC_SERIAL_CTL, AR9170_PHY_ADC_SCTL_SEL_EXTERNAL_RADIO);
90
91         delay(10);
92
93         set(0x1c589c, 0x00000000);      /*# 7-0 */
94         set(0x1c589c, 0x00000000);      /*# 15-8 */
95         set(0x1c589c, 0x00000000);      /*# 23-16 */
96         set(0x1c589c, 0x00000000);      /*# 31- */
97
98         set(0x1c589c, 0x00000000);      /*# 39- */
99         set(0x1c589c, 0x00000000);      /*# 47- */
100         set(0x1c589c, 0x00000000);      /*# 55- [48]:doubles the xtalosc bias current */
101         set(0x1c589c, 0x00000000);      /*# 63- */
102
103         set(0x1c589c, 0x00000000);      /*# 71- */
104         set(0x1c589c, 0x00000000);      /*# 79- */
105         set(0x1c589c, 0x00000000);      /*# 87- */
106         set(0x1c589c, 0x00000000);      /*# 95- */
107
108         set(0x1c589c, 0x00000000);      /*# 103- */
109         set(0x1c589c, 0x00000000);      /*# 111- */
110         set(0x1c589c, 0x00000000);      /*# 119- */
111         set(0x1c589c, 0x00000000);      /*# 127- */
112
113         set(0x1c589c, 0x00000000);      /*# 135- */
114         set(0x1c589c, 0x00000000);      /*# 143- */
115         set(0x1c589c, 0x00000000);      /*# 151- */
116         set(0x1c589c, 0x00000030);      /*# 159- #[158:156]=xlnabufmode */
117
118         set(0x1c589c, 0x00000004);      /*# 167-  [162]:disable clkp_driver to flow */
119         set(0x1c589c, 0x00000000);      /*# 175- */
120         set(0x1c589c, 0x00000000);      /*# 183-176 */
121         set(0x1c589c, 0x00000000);      /*# 191-184 */
122
123         set(0x1c589c, 0x00000000);      /*# 199- */
124         set(0x1c589c, 0x00000000);      /*# 207- */
125         set(0x1c589c, 0x00000000);      /*# 215- */
126         set(0x1c589c, 0x00000000);      /*# 223- */
127
128         set(0x1c589c, 0x00000000);      /*# 231- */
129         set(0x1c58c4, 0x00000000);      /*# 233-232 */
130
131         delay(10);
132
133         /* Select External Flow ???? (is internal addac??) */
134         set(AR9170_PHY_REG_ADC_SERIAL_CTL, AR9170_PHY_ADC_SCTL_SEL_INTERNAL_ADDAC);
135 }
136
137 static uint32_t AGC_calibration(uint32_t loop)
138 {
139         uint32_t wrdata;
140         uint32_t ret;
141
142 #define AGC_CAL_NF      (AR9170_PHY_AGC_CONTROL_CAL | AR9170_PHY_AGC_CONTROL_NF)
143
144         wrdata = get_async(AR9170_PHY_REG_AGC_CONTROL) | AGC_CAL_NF;
145         set(AR9170_PHY_REG_AGC_CONTROL, wrdata);
146
147         ret = get_async(AR9170_PHY_REG_AGC_CONTROL) & AGC_CAL_NF;
148
149         /* sitesurvey : 100 ms / current connected 200 ms */
150         while ((ret != 0) && loop--) {
151                 udelay(100);
152
153                 ret = get_async(AR9170_PHY_REG_AGC_CONTROL) & AGC_CAL_NF;
154         }
155
156         /* return the AGC/Noise calibration state to the driver */
157         return ret;
158 }
159
160 #define EIGHTY_FLAG (CARL9170FW_PHY_HT_ENABLE | CARL9170FW_PHY_HT_DYN2040)
161
162 static uint32_t rf_init(const uint32_t delta_slope_coeff_exp,
163                         const uint32_t delta_slope_coeff_man,
164                         const uint32_t delta_slope_coeff_exp_shgi,
165                         const uint32_t delta_slope_coeff_man_shgi,
166                         const uint32_t finiteLoopCount,
167                         const bool initialize)
168 {
169         uint32_t ret;
170
171         hw_turn_off_dyn(delta_slope_coeff_exp,
172                         delta_slope_coeff_man,
173                         delta_slope_coeff_exp_shgi,
174                         delta_slope_coeff_man_shgi);
175
176         if (initialize) {
177                 /* Real Chip */
178                 program_ADDAC();
179
180                 /* inverse chain 0 <-> chain 2 */
181                 set(AR9170_PHY_REG_ANALOG_SWAP, AR9170_PHY_ANALOG_SWAP_AB);
182
183                 /* swap chain 0 and chain 2 */
184                 set(AR9170_PHY_REG_ANALOG_SWAP, AR9170_PHY_ANALOG_SWAP_AB |
185                                                 AR9170_PHY_ANALOG_SWAP_ALT_CHAIN);
186
187                 /* Activate BB */
188                 set(AR9170_PHY_REG_ACTIVE, AR9170_PHY_ACTIVE_EN);
189                 delay(10);
190         }
191
192         ret = AGC_calibration(finiteLoopCount);
193
194         set_channel_end();
195         return ret;
196 }
197
198 void rf_cmd(const struct carl9170_cmd *cmd, struct carl9170_rsp *resp)
199 {
200         uint32_t ret;
201
202         fw.phy.ht_settings = cmd->rf_init.ht_settings;
203         fw.phy.frequency = cmd->rf_init.freq;
204
205         /*
206          * Is the clock controlled by the PHY?
207          */
208         if ((fw.phy.ht_settings & EIGHTY_FLAG) == EIGHTY_FLAG)
209                 clock_set(AHB_80_88MHZ, true);
210         else
211                 clock_set(AHB_40_44MHZ, true);
212
213         ret = rf_init(le32_to_cpu(cmd->rf_init.delta_slope_coeff_exp),
214                       le32_to_cpu(cmd->rf_init.delta_slope_coeff_man),
215                       le32_to_cpu(cmd->rf_init.delta_slope_coeff_exp_shgi),
216                       le32_to_cpu(cmd->rf_init.delta_slope_coeff_man_shgi),
217                       le32_to_cpu(cmd->rf_init.finiteLoopCount),
218                       cmd->hdr.cmd == CARL9170_CMD_RF_INIT);
219
220         resp->hdr.len = sizeof(struct carl9170_rf_init_result);
221         resp->rf_init_res.ret = cpu_to_le32(ret);
222 }
223
224 void rf_psm(void)
225 {
226         u32 bank3;
227
228         if (fw.phy.psm.state == CARL9170_PSM_SOFTWARE) {
229                 /* not enabled by the driver */
230                 return;
231         }
232
233         if (fw.phy.psm.state & CARL9170_PSM_SLEEP) {
234                 fw.phy.psm.state &= ~CARL9170_PSM_SLEEP;
235
236                 /* disable all agc gain and offset updates to a2 */
237                 set(AR9170_PHY_REG_TEST2, 0x8000000);
238
239                 /* power down ADDAC */
240                 set(AR9170_PHY_REG_ADC_CTL,
241                     AR9170_PHY_ADC_CTL_OFF_PWDDAC |
242                     AR9170_PHY_ADC_CTL_OFF_PWDADC |
243                     0xa0000000);
244
245                 /* Synthesizer off + RX off */
246                 bank3 = 0x00400018;
247
248                 fw.phy.state = CARL9170_PHY_OFF;
249         } else {
250                 /* advance to the next PSM step */
251                 fw.phy.psm.state--;
252
253                 if (fw.phy.psm.state == CARL9170_PSM_WAKE) {
254                         /* wake up ADDAC */
255                         set(AR9170_PHY_REG_ADC_CTL,
256                             AR9170_PHY_ADC_CTL_OFF_PWDDAC |
257                             AR9170_PHY_ADC_CTL_OFF_PWDADC);
258
259                         /* enable all agc gain and offset updates to a2 */
260                         set(AR9170_PHY_REG_TEST2, 0x0);
261
262                         /* Synthesizer on + RX on */
263                         bank3 = 0x01420098;
264
265                         fw.phy.state = CARL9170_PHY_ON;
266                 } else {
267                         return ;
268                 }
269         }
270
271         if (fw.phy.frequency < 3000000)
272                 bank3 |= 0x00800000;
273
274         set(0x1c58f0, bank3);
275 }
276
277 #endif /* CONFIG_CARL9170FW_RADIO_FUNCTIONS */