2 * carl9170 firmware - used by the ar9170 wireless device
4 * initialization and main() loop
6 * Copyright (c) 2000-2005 ZyDAS Technology Corporation
7 * Copyright (c) 2007-2009 Atheros Communications, Inc.
8 * Copyright 2009 Johannes Berg <johannes@sipsolutions.net>
9 * Copyright 2009-2011 Christian Lamparter <chunkeey@googlemail.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
35 #define AR9170_WATCH_DOG_TIMER 0x100
37 static void timer_init(const unsigned int timer, const unsigned int interval)
39 /* Set timer to periodic mode */
40 orl(AR9170_TIMER_REG_CONTROL, BIT(timer));
42 /* Set time interval */
43 set(AR9170_TIMER_REG_TIMER0 + (timer << 2), interval - 1);
45 /* Clear timer interrupt flag */
46 orl(AR9170_TIMER_REG_INTERRUPT, BIT(timer));
49 void clock_set(enum cpu_clock_t clock_, bool on)
53 * This setting does more than just mess with the CPU Clock.
54 * So watch out, if you need _stable_ timer interrupts.
56 #ifdef CONFIG_CARL9170FW_RADIO_FUNCTIONS
57 if (fw.phy.frequency < 3000000)
58 set(AR9170_PWR_REG_PLL_ADDAC, 0x5163);
60 set(AR9170_PWR_REG_PLL_ADDAC, 0x5143);
62 set(AR9170_PWR_REG_PLL_ADDAC, 0x5163);
63 #endif /* CONFIG_CARL9170FW_RADIO_FUNCTIONS */
65 fw.ticks_per_usec = GET_VAL(AR9170_PWR_PLL_ADDAC_DIV,
66 get(AR9170_PWR_REG_PLL_ADDAC));
68 set(AR9170_PWR_REG_CLOCK_SEL, (uint32_t) ((on ? 0x70 : 0x600) | clock_));
72 fw.ticks_per_usec >>= 1;
75 fw.ticks_per_usec >>= 1;
80 timer_init(1, (fw.ticks_per_usec * 25) >> 1);
83 static void init(void)
87 #ifdef CONFIG_CARL9170FW_DEBUG_UART
89 #endif /* CONFIG_CARL9170FW_DEBUG_UART */
91 /* 25/50/100ms timer (depends on cpu clock) */
97 /* initialize DMA memory */
98 memset(&dma_mem, 0, sizeof(dma_mem));
101 dma_init_descriptors();
103 /* clear all interrupt */
104 set(AR9170_MAC_REG_INT_CTRL, 0xffff);
106 orl(AR9170_MAC_REG_AFTER_PNP, 1);
108 /* Init watch dog control flag */
109 fw.watchdog_enable = 1;
111 set(AR9170_TIMER_REG_WATCH_DOG, AR9170_WATCH_DOG_TIMER);
113 #ifdef CONFIG_CARL9170FW_GPIO_INTERRUPT
114 fw.cached_gpio_state.gpio = get(AR9170_GPIO_REG_PORT_DATA) &
116 #endif /* CONFIG_CARL9170FW_GPIO_INTERRUPT */
118 /* this will get the downqueue moving. */
122 static void handle_fw(void)
124 if (fw.watchdog_enable == 1)
125 set(AR9170_TIMER_REG_WATCH_DOG, AR9170_WATCH_DOG_TIMER);
131 static void timer0_isr(void)
135 #ifdef CONFIG_CARL9170FW_GPIO_INTERRUPT
137 #endif /* CONFIG_CARL9170FW_GPIO_INTERRUPT */
139 #ifdef CONFIG_CARL9170FW_RADIO_FUNCTIONS
141 #endif /* CONFIG_CARL9170FW_RADIO_FUNCTIONS */
143 #ifdef CONFIG_CARL9170FW_DEBUG_LED_HEARTBEAT
144 set(AR9170_GPIO_REG_PORT_DATA, get(AR9170_GPIO_REG_PORT_DATA) ^ 1);
145 #endif /* CONFIG_CARL9170FW_DEBUG_LED_HEARTBEAT */
148 static void timer1_isr(void)
152 static void handle_timer(void)
156 intr = get(AR9170_TIMER_REG_INTERRUPT);
158 /* ACK timer interrupt */
159 set(AR9170_TIMER_REG_INTERRUPT, intr);
161 #define HANDLER(intr, flag, func) \
163 if ((intr & flag) != 0) { \
169 HANDLER(intr, BIT(0), timer0_isr);
171 HANDLER(intr, BIT(1), timer1_isr);
174 DBG("Unhandled Timer Event %x", (unsigned int) intr);
179 static void __noreturn main_loop(void)
186 * Due to frame order persevation, the wlan subroutines
187 * must be executed before handle_host_interface.
191 handle_host_interface();
202 * The bootcode will work with the device driver to load the firmware
203 * onto the device's Program SRAM. The Program SRAM has a size of 16 KB
204 * and also contains the stack, which grows down from 0x204000.
206 * The Program SRAM starts at address 0x200000 on the device.
207 * The firmware entry point (0x200004) is located in boot.S.
208 * we put _start() there with the linker script carl9170.lds.
211 void __section(boot) start(void)
213 clock_set(AHB_40MHZ_OSC, true);
215 /* watchdog magic pattern check */
216 if ((get(AR9170_PWR_REG_WATCH_DOG_MAGIC) & 0xffff0000) == 0x12340000) {
217 /* watch dog warm start */
218 incl(AR9170_PWR_REG_WATCH_DOG_MAGIC);
220 } else if ((get(AR9170_PWR_REG_WATCH_DOG_MAGIC) & 0xffff0000) == 0x98760000) {
224 /* write the magic pattern for watch dog */
225 andl(AR9170_PWR_REG_WATCH_DOG_MAGIC, 0xFFFF);
226 orl(AR9170_PWR_REG_WATCH_DOG_MAGIC, 0x12340000);
230 #ifdef CONFIG_CARL9170FW_DEBUG
233 BUG_ON(0x2b || !0x2b);
234 INFO("INFO MESSAGE");
236 /* a set of unique characters to detect transfer data corruptions */
237 DBG("AaBbCcDdEeFfGgHhIiJjKkLlMmNnOoPpQqRrSsTtUuVvWwXxYyZz"
238 " ~`!1@2#3$4%%5^6&7*8(9)0_-+={[}]|\\:;\"'<,>.?/");
239 #endif /* CONFIG_CARL9170FW_DEBUG */
242 * Tell the host, that the firmware has booted and is
243 * now ready to process requests.
245 send_cmd_to_host(0, CARL9170_RSP_BOOT, 0x00, NULL);