2 * carl9170 firmware - used by the ar9170 wireless device
4 * This module contains DMA descriptor related definitions.
6 * Copyright (c) 2000-2005 ZyDAS Technology Corporation
7 * Copyright (c) 2007-2009 Atheros Communications, Inc.
8 * Copyright 2009 Johannes Berg <johannes@sipsolutions.net>
9 * Copyright 2009-2011 Christian Lamparter <chunkeey@googlemail.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; If not, see <http://www.gnu.org/licenses/>.
25 #ifndef __CARL9170FW_DMA_H
26 #define __CARL9170FW_DMA_H
32 #include "ieee80211.h"
36 volatile uint16_t status; /* Descriptor status */
37 volatile uint16_t ctrl; /* Descriptor control */
38 volatile uint16_t dataSize; /* Data size */
39 volatile uint16_t totalLen; /* Total length */
40 struct dma_desc *lastAddr; /* Last address of this chain */
42 uint8_t *_dataAddr; /* Data buffer address */
45 struct dma_desc *nextAddr; /* Next TD address */
46 } __packed __aligned(4);
48 /* Up, Dn, 5x Tx, retry, Rx, [USB Int], (CAB), FW */
49 #define AR9170_TERMINATOR_NUMBER_B 10
51 #define AR9170_TERMINATOR_NUMBER_INT 1
53 #define AR9170_TERMINATOR_NUMBER_CAB CARL9170_INTF_NUM
55 #define AR9170_TERMINATOR_NUMBER (AR9170_TERMINATOR_NUMBER_B + \
56 AR9170_TERMINATOR_NUMBER_INT + \
57 AR9170_TERMINATOR_NUMBER_CAB)
59 #define AR9170_BLOCK_SIZE (256 + 64)
61 #define AR9170_DESCRIPTOR_SIZE (sizeof(struct dma_desc))
63 struct ar9170_tx_ba_frame {
64 struct ar9170_tx_hwdesc hdr;
65 struct ieee80211_ba ba;
68 struct carl9170_tx_ba_superframe {
69 struct carl9170_tx_superdesc s;
70 struct ar9170_tx_ba_frame f;
73 struct ar9170_tx_null_frame {
74 struct ar9170_tx_hwdesc hdr;
75 struct ieee80211_hdr null;
78 struct carl9170_tx_null_superframe {
79 struct carl9170_tx_superdesc s;
80 struct ar9170_tx_null_frame f;
83 #define CARL9170_BA_BUFFER_LEN (__roundup(sizeof(struct carl9170_tx_ba_superframe), 16))
84 #define CARL9170_RSP_BUFFER_LEN AR9170_BLOCK_SIZE
86 struct carl9170_sram_reserved {
88 uint32_t buf[CARL9170_BA_BUFFER_LEN / sizeof(uint32_t)];
89 struct carl9170_tx_ba_superframe ba;
93 uint32_t buf[CARL9170_MAX_CMD_LEN / sizeof(uint32_t)];
94 struct carl9170_cmd cmd;
96 #ifdef CONFIG_CARL9170FW_WOL
97 struct carl9170_tx_null_superframe null;
98 #endif /* CONFIG_CARL9170FW_WOL */
102 uint32_t buf[CARL9170_RSP_BUFFER_LEN / sizeof(uint32_t)];
103 struct carl9170_rsp rsp;
107 uint32_t buf[CARL9170_INTF_NUM][AR9170_MAC_BCN_LENGTH_MAX / sizeof(uint32_t)];
112 * Memory layout in RAM:
115 * | terminator descriptors (dma_desc)
116 * | - Up (to USB host)
117 * | - Down (from USB host)
118 * | - TX (5x, to wifi)
122 * | - FW cmd & req descriptor
123 * | - BlockAck descriptor
124 * | total: AR9170_TERMINATOR_NUMBER
126 * | block descriptors (dma_desc)
127 * | (AR9170_BLOCK_NUMBER)
128 * AR9170_BLOCK_BUFFER_BASE +-- align to multiple of 64
129 * | block buffers (AR9170_BLOCK_SIZE each)
130 * | (AR9170_BLOCK_NUMBER)
131 * approx. 0x117c00 +--
132 * | BA buffer (128 bytes)
134 * | CMD buffer (128 bytes)
135 * | - used as NULLFRAME buffer (128 bytes) for WOL
137 * | RSP buffer (320 bytes)
139 * | BEACON buffer (256 bytes)
141 * | unaccounted space / padding
146 #define CARL9170_SRAM_RESERVED (sizeof(struct carl9170_sram_reserved))
148 #define AR9170_FRAME_MEMORY_SIZE (AR9170_SRAM_SIZE - CARL9170_SRAM_RESERVED)
150 #define BLOCK_ALIGNMENT 64
152 #define NONBLOCK_DESCRIPTORS_SIZE \
153 (AR9170_DESCRIPTOR_SIZE * (AR9170_TERMINATOR_NUMBER))
155 #define NONBLOCK_DESCRIPTORS_SIZE_ALIGNED \
156 (ALIGN(NONBLOCK_DESCRIPTORS_SIZE, BLOCK_ALIGNMENT))
158 #define AR9170_BLOCK_NUMBER ((AR9170_FRAME_MEMORY_SIZE - NONBLOCK_DESCRIPTORS_SIZE_ALIGNED) / \
159 (AR9170_BLOCK_SIZE + AR9170_DESCRIPTOR_SIZE))
161 struct ar9170_data_block {
162 uint8_t data[AR9170_BLOCK_SIZE];
165 struct ar9170_dma_memory {
166 struct dma_desc terminator[AR9170_TERMINATOR_NUMBER];
167 struct dma_desc block[AR9170_BLOCK_NUMBER];
168 struct ar9170_data_block data[AR9170_BLOCK_NUMBER] __aligned(BLOCK_ALIGNMENT);
169 struct carl9170_sram_reserved reserved __aligned(BLOCK_ALIGNMENT);
172 extern struct ar9170_dma_memory dma_mem;
174 #define AR9170_DOWN_BLOCK_RATIO 2
175 #define AR9170_RX_BLOCK_RATIO 1
176 /* Tx 16*2 = 32 packets => 32*(5*320) */
177 #define AR9170_TX_BLOCK_NUMBER (AR9170_BLOCK_NUMBER * AR9170_DOWN_BLOCK_RATIO / \
178 (AR9170_RX_BLOCK_RATIO + AR9170_DOWN_BLOCK_RATIO))
179 #define AR9170_RX_BLOCK_NUMBER (AR9170_BLOCK_NUMBER - AR9170_TX_BLOCK_NUMBER)
182 #define AR9170_ERR_FS_BIT 1
183 #define AR9170_ERR_LS_BIT 2
184 #define AR9170_ERR_OWN_BITS 3
185 #define AR9170_ERR_DATA_SIZE 4
186 #define AR9170_ERR_TOTAL_LEN 5
187 #define AR9170_ERR_DATA 6
188 #define AR9170_ERR_SEQ 7
189 #define AR9170_ERR_LEN 8
191 /* Status bits definitions */
192 /* Own bits definitions */
193 #define AR9170_OWN_BITS 0x3
194 #define AR9170_OWN_BITS_S 0
195 #define AR9170_OWN_BITS_SW 0x0
196 #define AR9170_OWN_BITS_HW 0x1
197 #define AR9170_OWN_BITS_SE 0x2
199 /* Control bits definitions */
200 #define AR9170_CTRL_TXFAIL 1
201 #define AR9170_CTRL_BAFAIL 2
202 #define AR9170_CTRL_FAIL (AR9170_CTRL_TXFAIL | AR9170_CTRL_BAFAIL)
204 /* First segament bit */
205 #define AR9170_CTRL_LS_BIT 0x100
206 /* Last segament bit */
207 #define AR9170_CTRL_FS_BIT 0x200
210 struct dma_desc *head;
211 struct dma_desc *terminator;
214 #define DESC_PAYLOAD(a) ((void *)a->dataAddr)
215 #define DESC_PAYLOAD_OFF(a, offset) ((void *)((unsigned long)(a->_dataAddr) + offset))
217 struct dma_desc *dma_unlink_head(struct dma_queue *queue);
218 void dma_init_descriptors(void);
219 void dma_reclaim(struct dma_queue *q, struct dma_desc *desc);
220 void dma_put(struct dma_queue *q, struct dma_desc *desc);
222 static inline __inline bool is_terminator(struct dma_queue *q, struct dma_desc *desc)
224 return q->terminator == desc;
227 static inline __inline bool queue_empty(struct dma_queue *q)
229 return q->head == q->terminator;
233 * Get a completed packet with # descriptors. Return the first
234 * descriptor and pointer the head directly by lastAddr->nextAddr
236 static inline __inline struct dma_desc *dma_dequeue_bits(struct dma_queue *q,
239 struct dma_desc *desc = NULL;
241 if ((q->head->status & AR9170_OWN_BITS) == bits)
242 desc = dma_unlink_head(q);
247 static inline __inline struct dma_desc *dma_dequeue_not_bits(struct dma_queue *q,
250 struct dma_desc *desc = NULL;
252 /* AR9170_OWN_BITS_HW will be filtered out here too. */
253 if ((q->head->status & AR9170_OWN_BITS) != bits)
254 desc = dma_unlink_head(q);
259 #define for_each_desc_bits(desc, queue, bits) \
260 while ((desc = dma_dequeue_bits(queue, bits)))
262 #define for_each_desc_not_bits(desc, queue, bits) \
263 while ((desc = dma_dequeue_not_bits(queue, bits)))
265 #define for_each_desc(desc, queue) \
266 while ((desc = dma_unlink_head(queue)))
268 #define __for_each_desc_bits(desc, queue, bits) \
269 for (desc = (queue)->head; \
270 (desc != (queue)->terminator && \
271 (desc->status & AR9170_OWN_BITS) == bits); \
272 desc = desc->lastAddr->nextAddr)
274 #define __while_desc_bits(desc, queue, bits) \
275 for (desc = (queue)->head; \
276 (!queue_empty(queue) && \
277 (desc->status & AR9170_OWN_BITS) == bits); \
278 desc = (queue)->head)
280 #define __for_each_desc_continue(desc, queue) \
281 for (; desc != (queue)->terminator; \
282 desc = (desc)->lastAddr->nextAddr)
284 #define __for_each_desc(desc, queue) \
285 for (desc = (queue)->head; \
286 desc != (queue)->terminator; \
287 desc = (desc)->lastAddr->nextAddr)
289 #define __for_each_desc_safe(desc, tmp, queue) \
290 for (desc = (queue)->head, tmp = desc->lastAddr->nextAddr; \
291 desc != (queue)->terminator; \
292 desc = tmp, tmp = tmp->lastAddr->nextAddr)
294 #define __while_subdesc(desc, queue) \
295 for (desc = (queue)->head; \
296 desc != (queue)->terminator; \
297 desc = (desc)->nextAddr)
299 static inline __inline unsigned int queue_len(struct dma_queue *q)
301 struct dma_desc *desc;
304 __while_subdesc(desc, q)
311 * rearm a completed packet, so it will be processed agian.
313 static inline __inline void dma_rearm(struct dma_desc *desc)
315 /* Set OWN bit to HW */
316 desc->status = ((desc->status & (~AR9170_OWN_BITS)) |
320 static inline __inline void dma_fix_downqueue(struct dma_desc *desc)
322 desc->status = AR9170_OWN_BITS_HW;
325 desc->totalLen = AR9170_BLOCK_SIZE;
326 desc->lastAddr = desc;
329 static inline void __check_desc(void)
331 struct ar9170_dma_memory mem;
332 BUILD_BUG_ON(sizeof(struct ar9170_data_block) != AR9170_BLOCK_SIZE);
333 BUILD_BUG_ON(sizeof(struct dma_desc) != 20);
335 BUILD_BUG_ON(sizeof(mem) > AR9170_SRAM_SIZE);
337 BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, ba.buf) & (BLOCK_ALIGNMENT - 1));
338 BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, cmd.buf) & (BLOCK_ALIGNMENT - 1));
339 BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, rsp.buf) & (BLOCK_ALIGNMENT - 1));
340 BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, bcn.buf) & (BLOCK_ALIGNMENT - 1));
341 BUILD_BUG_ON(sizeof(struct carl9170_tx_null_superframe) > CARL9170_MAX_CMD_LEN);
344 #endif /* __CARL9170FW_DMA_H */