1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 1999 - 2010 Intel Corporation.
4 * Copyright (C) 2010 LAPIS SEMICONDUCTOR CO., LTD.
7 #include <linux/interrupt.h>
8 #include <linux/delay.h>
10 #include <linux/module.h>
11 #include <linux/sched.h>
12 #include <linux/pci.h>
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/errno.h>
16 #include <linux/netdevice.h>
17 #include <linux/skbuff.h>
18 #include <linux/can.h>
19 #include <linux/can/dev.h>
20 #include <linux/can/error.h>
22 #define PCH_CTRL_INIT BIT(0) /* The INIT bit of CANCONT register. */
23 #define PCH_CTRL_IE BIT(1) /* The IE bit of CAN control register */
24 #define PCH_CTRL_IE_SIE_EIE (BIT(3) | BIT(2) | BIT(1))
25 #define PCH_CTRL_CCE BIT(6)
26 #define PCH_CTRL_OPT BIT(7) /* The OPT bit of CANCONT register. */
27 #define PCH_OPT_SILENT BIT(3) /* The Silent bit of CANOPT reg. */
28 #define PCH_OPT_LBACK BIT(4) /* The LoopBack bit of CANOPT reg. */
30 #define PCH_CMASK_RX_TX_SET 0x00f3
31 #define PCH_CMASK_RX_TX_GET 0x0073
32 #define PCH_CMASK_ALL 0xff
33 #define PCH_CMASK_NEWDAT BIT(2)
34 #define PCH_CMASK_CLRINTPND BIT(3)
35 #define PCH_CMASK_CTRL BIT(4)
36 #define PCH_CMASK_ARB BIT(5)
37 #define PCH_CMASK_MASK BIT(6)
38 #define PCH_CMASK_RDWR BIT(7)
39 #define PCH_IF_MCONT_NEWDAT BIT(15)
40 #define PCH_IF_MCONT_MSGLOST BIT(14)
41 #define PCH_IF_MCONT_INTPND BIT(13)
42 #define PCH_IF_MCONT_UMASK BIT(12)
43 #define PCH_IF_MCONT_TXIE BIT(11)
44 #define PCH_IF_MCONT_RXIE BIT(10)
45 #define PCH_IF_MCONT_RMTEN BIT(9)
46 #define PCH_IF_MCONT_TXRQXT BIT(8)
47 #define PCH_IF_MCONT_EOB BIT(7)
48 #define PCH_IF_MCONT_DLC (BIT(0) | BIT(1) | BIT(2) | BIT(3))
49 #define PCH_MASK2_MDIR_MXTD (BIT(14) | BIT(15))
50 #define PCH_ID2_DIR BIT(13)
51 #define PCH_ID2_XTD BIT(14)
52 #define PCH_ID_MSGVAL BIT(15)
53 #define PCH_IF_CREQ_BUSY BIT(15)
55 #define PCH_STATUS_INT 0x8000
56 #define PCH_RP 0x00008000
57 #define PCH_REC 0x00007f00
58 #define PCH_TEC 0x000000ff
60 #define PCH_TX_OK BIT(3)
61 #define PCH_RX_OK BIT(4)
62 #define PCH_EPASSIV BIT(5)
63 #define PCH_EWARN BIT(6)
64 #define PCH_BUS_OFF BIT(7)
66 /* bit position of certain controller bits. */
67 #define PCH_BIT_BRP_SHIFT 0
68 #define PCH_BIT_SJW_SHIFT 6
69 #define PCH_BIT_TSEG1_SHIFT 8
70 #define PCH_BIT_TSEG2_SHIFT 12
71 #define PCH_BIT_BRPE_BRPE_SHIFT 6
73 #define PCH_MSK_BITT_BRP 0x3f
74 #define PCH_MSK_BRPE_BRPE 0x3c0
75 #define PCH_MSK_CTRL_IE_SIE_EIE 0x07
76 #define PCH_COUNTER_LIMIT 10
78 #define PCH_CAN_CLK 50000000 /* 50MHz */
81 * Define the number of message object.
82 * PCH CAN communications are done via Message RAM.
83 * The Message RAM consists of 32 message objects.
85 #define PCH_RX_OBJ_NUM 26
86 #define PCH_TX_OBJ_NUM 6
87 #define PCH_RX_OBJ_START 1
88 #define PCH_RX_OBJ_END PCH_RX_OBJ_NUM
89 #define PCH_TX_OBJ_START (PCH_RX_OBJ_END + 1)
90 #define PCH_TX_OBJ_END (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM)
92 #define PCH_FIFO_THRESH 16
94 /* TxRqst2 show status of MsgObjNo.17~32 */
95 #define PCH_TREQ2_TX_MASK (((1 << PCH_TX_OBJ_NUM) - 1) <<\
96 (PCH_RX_OBJ_END - 16))
122 struct pch_can_if_regs {
134 struct pch_can_regs {
143 struct pch_can_if_regs ifregs[2]; /* [0]=if1 [1]=if2 */
160 struct pch_can_priv {
163 u32 tx_enable[PCH_TX_OBJ_END];
164 u32 rx_enable[PCH_TX_OBJ_END];
165 u32 rx_link[PCH_TX_OBJ_END];
167 struct net_device *ndev;
168 struct pch_can_regs __iomem *regs;
169 struct napi_struct napi;
170 int tx_obj; /* Point next Tx Obj index */
174 static const struct can_bittiming_const pch_can_bittiming_const = {
175 .name = KBUILD_MODNAME,
182 .brp_max = 1024, /* 6bit + extended 4bit */
186 static const struct pci_device_id pch_pci_tbl[] = {
187 {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,},
190 MODULE_DEVICE_TABLE(pci, pch_pci_tbl);
192 static inline void pch_can_bit_set(void __iomem *addr, u32 mask)
194 iowrite32(ioread32(addr) | mask, addr);
197 static inline void pch_can_bit_clear(void __iomem *addr, u32 mask)
199 iowrite32(ioread32(addr) & ~mask, addr);
202 static void pch_can_set_run_mode(struct pch_can_priv *priv,
203 enum pch_can_mode mode)
207 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT);
211 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT);
215 netdev_err(priv->ndev, "%s -> Invalid Mode.\n", __func__);
220 static void pch_can_set_optmode(struct pch_can_priv *priv)
222 u32 reg_val = ioread32(&priv->regs->opt);
224 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
225 reg_val |= PCH_OPT_SILENT;
227 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
228 reg_val |= PCH_OPT_LBACK;
230 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT);
231 iowrite32(reg_val, &priv->regs->opt);
234 static void pch_can_rw_msg_obj(void __iomem *creq_addr, u32 num)
236 int counter = PCH_COUNTER_LIMIT;
239 iowrite32(num, creq_addr);
241 ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
248 pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
251 static void pch_can_set_int_enables(struct pch_can_priv *priv,
252 enum pch_can_mode interrupt_no)
254 switch (interrupt_no) {
255 case PCH_CAN_DISABLE:
256 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
260 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
264 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
268 netdev_err(priv->ndev, "Invalid interrupt number.\n");
273 static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
274 int set, enum pch_ifreg dir)
279 ie = PCH_IF_MCONT_TXIE;
281 ie = PCH_IF_MCONT_RXIE;
283 /* Reading the Msg buffer from Message RAM to IF1/2 registers. */
284 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
285 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
287 /* Setting the IF1/2MASK1 register to access MsgVal and RxIE bits */
288 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
289 &priv->regs->ifregs[dir].cmask);
292 /* Setting the MsgVal and RxIE/TxIE bits */
293 pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie);
294 pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
296 /* Clearing the MsgVal and RxIE/TxIE bits */
297 pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie);
298 pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
301 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
304 static void pch_can_set_rx_all(struct pch_can_priv *priv, int set)
308 /* Traversing to obtain the object configured as receivers. */
309 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++)
310 pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG);
313 static void pch_can_set_tx_all(struct pch_can_priv *priv, int set)
317 /* Traversing to obtain the object configured as transmit object. */
318 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
319 pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG);
322 static u32 pch_can_int_pending(struct pch_can_priv *priv)
324 return ioread32(&priv->regs->intr) & 0xffff;
327 static void pch_can_clear_if_buffers(struct pch_can_priv *priv)
329 int i; /* Msg Obj ID (1~32) */
331 for (i = PCH_RX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
332 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask);
333 iowrite32(0xffff, &priv->regs->ifregs[0].mask1);
334 iowrite32(0xffff, &priv->regs->ifregs[0].mask2);
335 iowrite32(0x0, &priv->regs->ifregs[0].id1);
336 iowrite32(0x0, &priv->regs->ifregs[0].id2);
337 iowrite32(0x0, &priv->regs->ifregs[0].mcont);
338 iowrite32(0x0, &priv->regs->ifregs[0].data[0]);
339 iowrite32(0x0, &priv->regs->ifregs[0].data[1]);
340 iowrite32(0x0, &priv->regs->ifregs[0].data[2]);
341 iowrite32(0x0, &priv->regs->ifregs[0].data[3]);
342 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
343 PCH_CMASK_ARB | PCH_CMASK_CTRL,
344 &priv->regs->ifregs[0].cmask);
345 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
349 static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
353 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
354 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
355 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
357 iowrite32(0x0, &priv->regs->ifregs[0].id1);
358 iowrite32(0x0, &priv->regs->ifregs[0].id2);
360 pch_can_bit_set(&priv->regs->ifregs[0].mcont,
363 /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
364 if (i == PCH_RX_OBJ_END)
365 pch_can_bit_set(&priv->regs->ifregs[0].mcont,
368 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
371 iowrite32(0, &priv->regs->ifregs[0].mask1);
372 pch_can_bit_clear(&priv->regs->ifregs[0].mask2,
373 0x1fff | PCH_MASK2_MDIR_MXTD);
375 /* Setting CMASK for writing */
376 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
377 PCH_CMASK_CTRL, &priv->regs->ifregs[0].cmask);
379 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
382 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
383 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
384 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
386 /* Resetting DIR bit for reception */
387 iowrite32(0x0, &priv->regs->ifregs[1].id1);
388 iowrite32(PCH_ID2_DIR, &priv->regs->ifregs[1].id2);
390 /* Setting EOB bit for transmitter */
391 iowrite32(PCH_IF_MCONT_EOB | PCH_IF_MCONT_UMASK,
392 &priv->regs->ifregs[1].mcont);
394 iowrite32(0, &priv->regs->ifregs[1].mask1);
395 pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff);
397 /* Setting CMASK for writing */
398 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
399 PCH_CMASK_CTRL, &priv->regs->ifregs[1].cmask);
401 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
405 static void pch_can_init(struct pch_can_priv *priv)
407 /* Stopping the Can device. */
408 pch_can_set_run_mode(priv, PCH_CAN_STOP);
410 /* Clearing all the message object buffers. */
411 pch_can_clear_if_buffers(priv);
413 /* Configuring the respective message object as either rx/tx object. */
414 pch_can_config_rx_tx_buffers(priv);
416 /* Enabling the interrupts. */
417 pch_can_set_int_enables(priv, PCH_CAN_ALL);
420 static void pch_can_release(struct pch_can_priv *priv)
422 /* Stooping the CAN device. */
423 pch_can_set_run_mode(priv, PCH_CAN_STOP);
425 /* Disabling the interrupts. */
426 pch_can_set_int_enables(priv, PCH_CAN_NONE);
428 /* Disabling all the receive object. */
429 pch_can_set_rx_all(priv, 0);
431 /* Disabling all the transmit object. */
432 pch_can_set_tx_all(priv, 0);
435 /* This function clears interrupt(s) from the CAN device. */
436 static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
438 /* Clear interrupt for transmit object */
439 if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) {
440 /* Setting CMASK for clearing the reception interrupts. */
441 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
442 &priv->regs->ifregs[0].cmask);
444 /* Clearing the Dir bit. */
445 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
447 /* Clearing NewDat & IntPnd */
448 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
449 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
451 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask);
452 } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) {
454 * Setting CMASK for clearing interrupts for frame transmission.
456 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
457 &priv->regs->ifregs[1].cmask);
459 /* Resetting the ID registers. */
460 pch_can_bit_set(&priv->regs->ifregs[1].id2,
461 PCH_ID2_DIR | (0x7ff << 2));
462 iowrite32(0x0, &priv->regs->ifregs[1].id1);
464 /* Clearing NewDat, TxRqst & IntPnd */
465 pch_can_bit_clear(&priv->regs->ifregs[1].mcont,
466 PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
467 PCH_IF_MCONT_TXRQXT);
468 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, mask);
472 static void pch_can_reset(struct pch_can_priv *priv)
474 /* write to sw reset register */
475 iowrite32(1, &priv->regs->srst);
476 iowrite32(0, &priv->regs->srst);
479 static void pch_can_error(struct net_device *ndev, u32 status)
482 struct pch_can_priv *priv = netdev_priv(ndev);
483 struct can_frame *cf;
485 struct net_device_stats *stats = &(priv->ndev->stats);
486 enum can_state state = priv->can.state;
488 skb = alloc_can_err_skb(ndev, &cf);
492 if (status & PCH_BUS_OFF) {
493 pch_can_set_tx_all(priv, 0);
494 pch_can_set_rx_all(priv, 0);
495 state = CAN_STATE_BUS_OFF;
496 cf->can_id |= CAN_ERR_BUSOFF;
497 priv->can.can_stats.bus_off++;
501 errc = ioread32(&priv->regs->errc);
502 /* Warning interrupt. */
503 if (status & PCH_EWARN) {
504 state = CAN_STATE_ERROR_WARNING;
505 priv->can.can_stats.error_warning++;
506 cf->can_id |= CAN_ERR_CRTL;
507 if (((errc & PCH_REC) >> 8) > 96)
508 cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
509 if ((errc & PCH_TEC) > 96)
510 cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
512 "%s -> Error Counter is more than 96.\n", __func__);
514 /* Error passive interrupt. */
515 if (status & PCH_EPASSIV) {
516 priv->can.can_stats.error_passive++;
517 state = CAN_STATE_ERROR_PASSIVE;
518 cf->can_id |= CAN_ERR_CRTL;
520 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
521 if ((errc & PCH_TEC) > 127)
522 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
524 "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
527 lec = status & PCH_LEC_ALL;
530 cf->data[2] |= CAN_ERR_PROT_STUFF;
531 priv->can.can_stats.bus_error++;
535 cf->data[2] |= CAN_ERR_PROT_FORM;
536 priv->can.can_stats.bus_error++;
540 cf->can_id |= CAN_ERR_ACK;
541 priv->can.can_stats.bus_error++;
546 cf->data[2] |= CAN_ERR_PROT_BIT;
547 priv->can.can_stats.bus_error++;
551 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
552 priv->can.can_stats.bus_error++;
555 case PCH_LEC_ALL: /* Written by CPU. No error status */
559 cf->data[6] = errc & PCH_TEC;
560 cf->data[7] = (errc & PCH_REC) >> 8;
562 priv->can.state = state;
563 netif_receive_skb(skb);
566 static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
568 struct net_device *ndev = (struct net_device *)dev_id;
569 struct pch_can_priv *priv = netdev_priv(ndev);
571 if (!pch_can_int_pending(priv))
574 pch_can_set_int_enables(priv, PCH_CAN_NONE);
575 napi_schedule(&priv->napi);
579 static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
581 if (obj_id < PCH_FIFO_THRESH) {
582 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
583 PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask);
585 /* Clearing the Dir bit. */
586 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
588 /* Clearing NewDat & IntPnd */
589 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
590 PCH_IF_MCONT_INTPND);
591 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
592 } else if (obj_id > PCH_FIFO_THRESH) {
593 pch_can_int_clr(priv, obj_id);
594 } else if (obj_id == PCH_FIFO_THRESH) {
596 for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
597 pch_can_int_clr(priv, cnt + 1);
601 static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
603 struct pch_can_priv *priv = netdev_priv(ndev);
604 struct net_device_stats *stats = &(priv->ndev->stats);
606 struct can_frame *cf;
608 netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n");
609 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
610 PCH_IF_MCONT_MSGLOST);
611 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
612 &priv->regs->ifregs[0].cmask);
613 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
615 skb = alloc_can_err_skb(ndev, &cf);
619 cf->can_id |= CAN_ERR_CRTL;
620 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
621 stats->rx_over_errors++;
624 netif_receive_skb(skb);
627 static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
633 struct can_frame *cf;
634 struct pch_can_priv *priv = netdev_priv(ndev);
635 struct net_device_stats *stats = &(priv->ndev->stats);
641 /* Reading the message object from the Message RAM */
642 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
643 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_num);
645 /* Reading the MCONT register. */
646 reg = ioread32(&priv->regs->ifregs[0].mcont);
648 if (reg & PCH_IF_MCONT_EOB)
651 /* If MsgLost bit set. */
652 if (reg & PCH_IF_MCONT_MSGLOST) {
653 pch_can_rx_msg_lost(ndev, obj_num);
658 } else if (!(reg & PCH_IF_MCONT_NEWDAT)) {
663 skb = alloc_can_skb(priv->ndev, &cf);
665 netdev_err(ndev, "alloc_can_skb Failed\n");
669 /* Get Received data */
670 id2 = ioread32(&priv->regs->ifregs[0].id2);
671 if (id2 & PCH_ID2_XTD) {
672 id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff);
673 id |= (((id2) & 0x1fff) << 16);
674 cf->can_id = id | CAN_EFF_FLAG;
676 id = (id2 >> 2) & CAN_SFF_MASK;
680 cf->len = can_cc_dlc2len((ioread32(&priv->regs->
681 ifregs[0].mcont)) & 0xF);
683 if (id2 & PCH_ID2_DIR) {
684 cf->can_id |= CAN_RTR_FLAG;
686 for (i = 0; i < cf->len; i += 2) {
687 data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]);
688 cf->data[i] = data_reg;
689 cf->data[i + 1] = data_reg >> 8;
692 stats->rx_bytes += cf->len;
697 netif_receive_skb(skb);
699 pch_fifo_thresh(priv, obj_num);
706 static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
708 struct pch_can_priv *priv = netdev_priv(ndev);
709 struct net_device_stats *stats = &(priv->ndev->stats);
711 stats->tx_bytes += can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1,
714 iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
715 &priv->regs->ifregs[1].cmask);
716 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, int_stat);
717 if (int_stat == PCH_TX_OBJ_END)
718 netif_wake_queue(ndev);
721 static int pch_can_poll(struct napi_struct *napi, int quota)
723 struct net_device *ndev = napi->dev;
724 struct pch_can_priv *priv = netdev_priv(ndev);
727 int quota_save = quota;
729 int_stat = pch_can_int_pending(priv);
733 if (int_stat == PCH_STATUS_INT) {
734 reg_stat = ioread32(&priv->regs->stat);
736 if ((reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) &&
737 ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL)) {
738 pch_can_error(ndev, reg_stat);
742 if (reg_stat & (PCH_TX_OK | PCH_RX_OK))
743 pch_can_bit_clear(&priv->regs->stat,
744 reg_stat & (PCH_TX_OK | PCH_RX_OK));
746 int_stat = pch_can_int_pending(priv);
752 if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) {
753 quota -= pch_can_rx_normal(ndev, int_stat, quota);
754 } else if ((int_stat >= PCH_TX_OBJ_START) &&
755 (int_stat <= PCH_TX_OBJ_END)) {
756 /* Handle transmission interrupt */
757 pch_can_tx_complete(ndev, int_stat);
762 pch_can_set_int_enables(priv, PCH_CAN_ALL);
764 return quota_save - quota;
767 static int pch_set_bittiming(struct net_device *ndev)
769 struct pch_can_priv *priv = netdev_priv(ndev);
770 const struct can_bittiming *bt = &priv->can.bittiming;
774 /* Setting the CCE bit for accessing the Can Timing register. */
775 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE);
777 canbit = (bt->brp - 1) & PCH_MSK_BITT_BRP;
778 canbit |= (bt->sjw - 1) << PCH_BIT_SJW_SHIFT;
779 canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1_SHIFT;
780 canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2_SHIFT;
781 bepe = ((bt->brp - 1) & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE_SHIFT;
782 iowrite32(canbit, &priv->regs->bitt);
783 iowrite32(bepe, &priv->regs->brpe);
784 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
789 static void pch_can_start(struct net_device *ndev)
791 struct pch_can_priv *priv = netdev_priv(ndev);
793 if (priv->can.state != CAN_STATE_STOPPED)
796 pch_set_bittiming(ndev);
797 pch_can_set_optmode(priv);
799 pch_can_set_tx_all(priv, 1);
800 pch_can_set_rx_all(priv, 1);
802 /* Setting the CAN to run mode. */
803 pch_can_set_run_mode(priv, PCH_CAN_RUN);
805 priv->can.state = CAN_STATE_ERROR_ACTIVE;
810 static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
817 netif_wake_queue(ndev);
827 static int pch_can_open(struct net_device *ndev)
829 struct pch_can_priv *priv = netdev_priv(ndev);
832 /* Registering the interrupt. */
833 retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
836 netdev_err(ndev, "request_irq failed.\n");
840 /* Open common can device */
841 retval = open_candev(ndev);
843 netdev_err(ndev, "open_candev() failed %d\n", retval);
844 goto err_open_candev;
849 napi_enable(&priv->napi);
850 netif_start_queue(ndev);
855 free_irq(priv->dev->irq, ndev);
857 pch_can_release(priv);
862 static int pch_close(struct net_device *ndev)
864 struct pch_can_priv *priv = netdev_priv(ndev);
866 netif_stop_queue(ndev);
867 napi_disable(&priv->napi);
868 pch_can_release(priv);
869 free_irq(priv->dev->irq, ndev);
871 priv->can.state = CAN_STATE_STOPPED;
875 static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
877 struct pch_can_priv *priv = netdev_priv(ndev);
878 struct can_frame *cf = (struct can_frame *)skb->data;
883 if (can_dropped_invalid_skb(ndev, skb))
886 tx_obj_no = priv->tx_obj;
887 if (priv->tx_obj == PCH_TX_OBJ_END) {
888 if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK)
889 netif_stop_queue(ndev);
891 priv->tx_obj = PCH_TX_OBJ_START;
896 /* Setting the CMASK register. */
897 pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL);
899 /* If ID extended is set. */
900 if (cf->can_id & CAN_EFF_FLAG) {
901 iowrite32(cf->can_id & 0xffff, &priv->regs->ifregs[1].id1);
902 id2 = ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD;
904 iowrite32(0, &priv->regs->ifregs[1].id1);
905 id2 = (cf->can_id & CAN_SFF_MASK) << 2;
908 id2 |= PCH_ID_MSGVAL;
910 /* If remote frame has to be transmitted.. */
911 if (!(cf->can_id & CAN_RTR_FLAG))
914 iowrite32(id2, &priv->regs->ifregs[1].id2);
916 /* Copy data to register */
917 for (i = 0; i < cf->len; i += 2) {
918 iowrite16(cf->data[i] | (cf->data[i + 1] << 8),
919 &priv->regs->ifregs[1].data[i / 2]);
922 can_put_echo_skb(skb, ndev, tx_obj_no - PCH_RX_OBJ_END - 1, 0);
924 /* Set the size of the data. Update if2_mcont */
925 iowrite32(cf->len | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT |
926 PCH_IF_MCONT_TXIE, &priv->regs->ifregs[1].mcont);
928 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no);
933 static const struct net_device_ops pch_can_netdev_ops = {
934 .ndo_open = pch_can_open,
935 .ndo_stop = pch_close,
936 .ndo_start_xmit = pch_xmit,
937 .ndo_change_mtu = can_change_mtu,
940 static void pch_can_remove(struct pci_dev *pdev)
942 struct net_device *ndev = pci_get_drvdata(pdev);
943 struct pch_can_priv *priv = netdev_priv(ndev);
945 unregister_candev(priv->ndev);
947 pci_disable_msi(priv->dev);
948 pci_release_regions(pdev);
949 pci_disable_device(pdev);
951 pci_iounmap(pdev, priv->regs);
952 free_candev(priv->ndev);
955 static void __maybe_unused pch_can_set_int_custom(struct pch_can_priv *priv)
957 /* Clearing the IE, SIE and EIE bits of Can control register. */
958 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
960 /* Appropriately setting them. */
961 pch_can_bit_set(&priv->regs->cont,
962 ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
965 /* This function retrieves interrupt enabled for the CAN device. */
966 static u32 __maybe_unused pch_can_get_int_enables(struct pch_can_priv *priv)
968 /* Obtaining the status of IE, SIE and EIE interrupt bits. */
969 return (ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1;
972 static u32 __maybe_unused pch_can_get_rxtx_ir(struct pch_can_priv *priv,
973 u32 buff_num, enum pch_ifreg dir)
978 ie = PCH_IF_MCONT_RXIE;
980 ie = PCH_IF_MCONT_TXIE;
982 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
983 pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
985 if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
986 ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie))
994 static void __maybe_unused pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
995 u32 buffer_num, int set)
997 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
998 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
999 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
1000 &priv->regs->ifregs[0].cmask);
1002 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
1005 pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
1007 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
1010 static u32 __maybe_unused pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
1015 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
1016 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
1018 if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
1025 static int __maybe_unused pch_can_get_buffer_status(struct pch_can_priv *priv)
1027 return (ioread32(&priv->regs->treq1) & 0xffff) |
1028 (ioread32(&priv->regs->treq2) << 16);
1031 static int __maybe_unused pch_can_suspend(struct device *dev_d)
1034 u32 buf_stat; /* Variable for reading the transmit buffer status. */
1035 int counter = PCH_COUNTER_LIMIT;
1037 struct net_device *dev = dev_get_drvdata(dev_d);
1038 struct pch_can_priv *priv = netdev_priv(dev);
1040 /* Stop the CAN controller */
1041 pch_can_set_run_mode(priv, PCH_CAN_STOP);
1043 /* Indicate that we are aboutto/in suspend */
1044 priv->can.state = CAN_STATE_STOPPED;
1046 /* Waiting for all transmission to complete. */
1048 buf_stat = pch_can_get_buffer_status(priv);
1055 dev_err(dev_d, "%s -> Transmission time out.\n", __func__);
1057 /* Save interrupt configuration and then disable them */
1058 priv->int_enables = pch_can_get_int_enables(priv);
1059 pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1061 /* Save Tx buffer enable state */
1062 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
1063 priv->tx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i,
1066 /* Disable all Transmit buffers */
1067 pch_can_set_tx_all(priv, 0);
1069 /* Save Rx buffer enable state */
1070 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
1071 priv->rx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i,
1073 priv->rx_link[i - 1] = pch_can_get_rx_buffer_link(priv, i);
1076 /* Disable all Receive buffers */
1077 pch_can_set_rx_all(priv, 0);
1082 static int __maybe_unused pch_can_resume(struct device *dev_d)
1085 struct net_device *dev = dev_get_drvdata(dev_d);
1086 struct pch_can_priv *priv = netdev_priv(dev);
1088 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1090 /* Disabling all interrupts. */
1091 pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1093 /* Setting the CAN device in Stop Mode. */
1094 pch_can_set_run_mode(priv, PCH_CAN_STOP);
1096 /* Configuring the transmit and receive buffers. */
1097 pch_can_config_rx_tx_buffers(priv);
1099 /* Restore the CAN state */
1100 pch_set_bittiming(dev);
1103 pch_can_set_optmode(priv);
1105 /* Enabling the transmit buffer. */
1106 for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
1107 pch_can_set_rxtx(priv, i, priv->tx_enable[i - 1], PCH_TX_IFREG);
1109 /* Configuring the receive buffer and enabling them. */
1110 for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
1111 /* Restore buffer link */
1112 pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i - 1]);
1114 /* Restore buffer enables */
1115 pch_can_set_rxtx(priv, i, priv->rx_enable[i - 1], PCH_RX_IFREG);
1118 /* Enable CAN Interrupts */
1119 pch_can_set_int_custom(priv);
1121 /* Restore Run Mode */
1122 pch_can_set_run_mode(priv, PCH_CAN_RUN);
1127 static int pch_can_get_berr_counter(const struct net_device *dev,
1128 struct can_berr_counter *bec)
1130 struct pch_can_priv *priv = netdev_priv(dev);
1131 u32 errc = ioread32(&priv->regs->errc);
1133 bec->txerr = errc & PCH_TEC;
1134 bec->rxerr = (errc & PCH_REC) >> 8;
1139 static int pch_can_probe(struct pci_dev *pdev,
1140 const struct pci_device_id *id)
1142 struct net_device *ndev;
1143 struct pch_can_priv *priv;
1147 rc = pci_enable_device(pdev);
1149 dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc);
1150 goto probe_exit_endev;
1153 rc = pci_request_regions(pdev, KBUILD_MODNAME);
1155 dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc);
1156 goto probe_exit_pcireq;
1159 addr = pci_iomap(pdev, 1, 0);
1162 dev_err(&pdev->dev, "Failed pci_iomap\n");
1163 goto probe_exit_ipmap;
1166 ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END);
1169 dev_err(&pdev->dev, "Failed alloc_candev\n");
1170 goto probe_exit_alloc_candev;
1173 priv = netdev_priv(ndev);
1177 priv->can.bittiming_const = &pch_can_bittiming_const;
1178 priv->can.do_set_mode = pch_can_do_set_mode;
1179 priv->can.do_get_berr_counter = pch_can_get_berr_counter;
1180 priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
1181 CAN_CTRLMODE_LOOPBACK;
1182 priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */
1184 ndev->irq = pdev->irq;
1185 ndev->flags |= IFF_ECHO;
1187 pci_set_drvdata(pdev, ndev);
1188 SET_NETDEV_DEV(ndev, &pdev->dev);
1189 ndev->netdev_ops = &pch_can_netdev_ops;
1190 priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
1192 netif_napi_add_weight(ndev, &priv->napi, pch_can_poll, PCH_RX_OBJ_END);
1194 rc = pci_enable_msi(priv->dev);
1196 netdev_err(ndev, "PCH CAN opened without MSI\n");
1199 netdev_err(ndev, "PCH CAN opened with MSI\n");
1200 pci_set_master(pdev);
1204 rc = register_candev(ndev);
1206 dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
1207 goto probe_exit_reg_candev;
1212 probe_exit_reg_candev:
1214 pci_disable_msi(priv->dev);
1216 probe_exit_alloc_candev:
1217 pci_iounmap(pdev, addr);
1219 pci_release_regions(pdev);
1221 pci_disable_device(pdev);
1226 static SIMPLE_DEV_PM_OPS(pch_can_pm_ops,
1230 static struct pci_driver pch_can_pci_driver = {
1232 .id_table = pch_pci_tbl,
1233 .probe = pch_can_probe,
1234 .remove = pch_can_remove,
1235 .driver.pm = &pch_can_pm_ops,
1238 module_pci_driver(pch_can_pci_driver);
1240 MODULE_DESCRIPTION("Intel EG20T PCH CAN(Controller Area Network) Driver");
1241 MODULE_LICENSE("GPL v2");
1242 MODULE_VERSION("0.94");