1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91_can.c - CAN network driver for AT91 SoC CAN controller
5 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
6 * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de>
10 #include <linux/errno.h>
11 #include <linux/if_arp.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/netdevice.h>
17 #include <linux/platform_device.h>
18 #include <linux/rtnetlink.h>
19 #include <linux/skbuff.h>
20 #include <linux/spinlock.h>
21 #include <linux/string.h>
22 #include <linux/types.h>
24 #include <linux/can/dev.h>
25 #include <linux/can/error.h>
27 #define AT91_MB_MASK(i) ((1 << (i)) - 1)
29 /* Common registers */
44 /* Mailbox registers (0 <= i <= 15) */
45 #define AT91_MMR(i) ((enum at91_reg)(0x200 + ((i) * 0x20)))
46 #define AT91_MAM(i) ((enum at91_reg)(0x204 + ((i) * 0x20)))
47 #define AT91_MID(i) ((enum at91_reg)(0x208 + ((i) * 0x20)))
48 #define AT91_MFID(i) ((enum at91_reg)(0x20C + ((i) * 0x20)))
49 #define AT91_MSR(i) ((enum at91_reg)(0x210 + ((i) * 0x20)))
50 #define AT91_MDL(i) ((enum at91_reg)(0x214 + ((i) * 0x20)))
51 #define AT91_MDH(i) ((enum at91_reg)(0x218 + ((i) * 0x20)))
52 #define AT91_MCR(i) ((enum at91_reg)(0x21C + ((i) * 0x20)))
55 #define AT91_MR_CANEN BIT(0)
56 #define AT91_MR_LPM BIT(1)
57 #define AT91_MR_ABM BIT(2)
58 #define AT91_MR_OVL BIT(3)
59 #define AT91_MR_TEOF BIT(4)
60 #define AT91_MR_TTM BIT(5)
61 #define AT91_MR_TIMFRZ BIT(6)
62 #define AT91_MR_DRPT BIT(7)
64 #define AT91_SR_RBSY BIT(29)
66 #define AT91_MMR_PRIO_SHIFT (16)
68 #define AT91_MID_MIDE BIT(29)
70 #define AT91_MSR_MRTR BIT(20)
71 #define AT91_MSR_MABT BIT(22)
72 #define AT91_MSR_MRDY BIT(23)
73 #define AT91_MSR_MMI BIT(24)
75 #define AT91_MCR_MRTR BIT(20)
76 #define AT91_MCR_MTCR BIT(23)
80 AT91_MB_MODE_DISABLED = 0,
82 AT91_MB_MODE_RX_OVRWR = 2,
84 AT91_MB_MODE_CONSUMER = 4,
85 AT91_MB_MODE_PRODUCER = 5,
88 /* Interrupt mask bits */
89 #define AT91_IRQ_ERRA BIT(16)
90 #define AT91_IRQ_WARN BIT(17)
91 #define AT91_IRQ_ERRP BIT(18)
92 #define AT91_IRQ_BOFF BIT(19)
93 #define AT91_IRQ_SLEEP BIT(20)
94 #define AT91_IRQ_WAKEUP BIT(21)
95 #define AT91_IRQ_TOVF BIT(22)
96 #define AT91_IRQ_TSTP BIT(23)
97 #define AT91_IRQ_CERR BIT(24)
98 #define AT91_IRQ_SERR BIT(25)
99 #define AT91_IRQ_AERR BIT(26)
100 #define AT91_IRQ_FERR BIT(27)
101 #define AT91_IRQ_BERR BIT(28)
103 #define AT91_IRQ_ERR_ALL (0x1fff0000)
104 #define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \
105 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR)
106 #define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \
107 AT91_IRQ_ERRP | AT91_IRQ_BOFF)
109 #define AT91_IRQ_ALL (0x1fffffff)
112 AT91_DEVTYPE_SAM9263,
116 struct at91_devtype_data {
117 unsigned int rx_first;
118 unsigned int rx_split;
119 unsigned int rx_last;
120 unsigned int tx_shift;
121 enum at91_devtype type;
125 struct can_priv can; /* must be the first member! */
126 struct napi_struct napi;
128 void __iomem *reg_base;
131 unsigned int tx_next;
132 unsigned int tx_echo;
133 unsigned int rx_next;
134 struct at91_devtype_data devtype_data;
137 struct at91_can_data *pdata;
142 static const struct at91_devtype_data at91_at91sam9263_data = {
147 .type = AT91_DEVTYPE_SAM9263,
150 static const struct at91_devtype_data at91_at91sam9x5_data = {
155 .type = AT91_DEVTYPE_SAM9X5,
158 static const struct can_bittiming_const at91_bittiming_const = {
159 .name = KBUILD_MODNAME,
170 #define AT91_IS(_model) \
171 static inline int __maybe_unused at91_is_sam##_model(const struct at91_priv *priv) \
173 return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \
179 static inline unsigned int get_mb_rx_first(const struct at91_priv *priv)
181 return priv->devtype_data.rx_first;
184 static inline unsigned int get_mb_rx_last(const struct at91_priv *priv)
186 return priv->devtype_data.rx_last;
189 static inline unsigned int get_mb_rx_split(const struct at91_priv *priv)
191 return priv->devtype_data.rx_split;
194 static inline unsigned int get_mb_rx_num(const struct at91_priv *priv)
196 return get_mb_rx_last(priv) - get_mb_rx_first(priv) + 1;
199 static inline unsigned int get_mb_rx_low_last(const struct at91_priv *priv)
201 return get_mb_rx_split(priv) - 1;
204 static inline unsigned int get_mb_rx_low_mask(const struct at91_priv *priv)
206 return AT91_MB_MASK(get_mb_rx_split(priv)) &
207 ~AT91_MB_MASK(get_mb_rx_first(priv));
210 static inline unsigned int get_mb_tx_shift(const struct at91_priv *priv)
212 return priv->devtype_data.tx_shift;
215 static inline unsigned int get_mb_tx_num(const struct at91_priv *priv)
217 return 1 << get_mb_tx_shift(priv);
220 static inline unsigned int get_mb_tx_first(const struct at91_priv *priv)
222 return get_mb_rx_last(priv) + 1;
225 static inline unsigned int get_mb_tx_last(const struct at91_priv *priv)
227 return get_mb_tx_first(priv) + get_mb_tx_num(priv) - 1;
230 static inline unsigned int get_next_prio_shift(const struct at91_priv *priv)
232 return get_mb_tx_shift(priv);
235 static inline unsigned int get_next_prio_mask(const struct at91_priv *priv)
237 return 0xf << get_mb_tx_shift(priv);
240 static inline unsigned int get_next_mb_mask(const struct at91_priv *priv)
242 return AT91_MB_MASK(get_mb_tx_shift(priv));
245 static inline unsigned int get_next_mask(const struct at91_priv *priv)
247 return get_next_mb_mask(priv) | get_next_prio_mask(priv);
250 static inline unsigned int get_irq_mb_rx(const struct at91_priv *priv)
252 return AT91_MB_MASK(get_mb_rx_last(priv) + 1) &
253 ~AT91_MB_MASK(get_mb_rx_first(priv));
256 static inline unsigned int get_irq_mb_tx(const struct at91_priv *priv)
258 return AT91_MB_MASK(get_mb_tx_last(priv) + 1) &
259 ~AT91_MB_MASK(get_mb_tx_first(priv));
262 static inline unsigned int get_tx_next_mb(const struct at91_priv *priv)
264 return (priv->tx_next & get_next_mb_mask(priv)) + get_mb_tx_first(priv);
267 static inline unsigned int get_tx_next_prio(const struct at91_priv *priv)
269 return (priv->tx_next >> get_next_prio_shift(priv)) & 0xf;
272 static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv)
274 return (priv->tx_echo & get_next_mb_mask(priv)) + get_mb_tx_first(priv);
277 static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg)
279 return readl_relaxed(priv->reg_base + reg);
282 static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg,
285 writel_relaxed(value, priv->reg_base + reg);
288 static inline void set_mb_mode_prio(const struct at91_priv *priv,
289 unsigned int mb, enum at91_mb_mode mode,
292 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16));
295 static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb,
296 enum at91_mb_mode mode)
298 set_mb_mode_prio(priv, mb, mode, 0);
301 static inline u32 at91_can_id_to_reg_mid(canid_t can_id)
305 if (can_id & CAN_EFF_FLAG)
306 reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE;
308 reg_mid = (can_id & CAN_SFF_MASK) << 18;
313 static void at91_setup_mailboxes(struct net_device *dev)
315 struct at91_priv *priv = netdev_priv(dev);
319 /* Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first
320 * mailbox is disabled. The next 11 mailboxes are used as a
321 * reception FIFO. The last mailbox is configured with
322 * overwrite option. The overwrite flag indicates a FIFO
325 reg_mid = at91_can_id_to_reg_mid(priv->mb0_id);
326 for (i = 0; i < get_mb_rx_first(priv); i++) {
327 set_mb_mode(priv, i, AT91_MB_MODE_DISABLED);
328 at91_write(priv, AT91_MID(i), reg_mid);
329 at91_write(priv, AT91_MCR(i), 0x0); /* clear dlc */
332 for (i = get_mb_rx_first(priv); i < get_mb_rx_last(priv); i++)
333 set_mb_mode(priv, i, AT91_MB_MODE_RX);
334 set_mb_mode(priv, get_mb_rx_last(priv), AT91_MB_MODE_RX_OVRWR);
336 /* reset acceptance mask and id register */
337 for (i = get_mb_rx_first(priv); i <= get_mb_rx_last(priv); i++) {
338 at91_write(priv, AT91_MAM(i), 0x0);
339 at91_write(priv, AT91_MID(i), AT91_MID_MIDE);
342 /* The last 4 mailboxes are used for transmitting. */
343 for (i = get_mb_tx_first(priv); i <= get_mb_tx_last(priv); i++)
344 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0);
346 /* Reset tx and rx helper pointers */
347 priv->tx_next = priv->tx_echo = 0;
348 priv->rx_next = get_mb_rx_first(priv);
351 static int at91_set_bittiming(struct net_device *dev)
353 const struct at91_priv *priv = netdev_priv(dev);
354 const struct can_bittiming *bt = &priv->can.bittiming;
357 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) |
358 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) |
359 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) |
360 ((bt->phase_seg2 - 1) << 0);
362 netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br);
364 at91_write(priv, AT91_BR, reg_br);
369 static int at91_get_berr_counter(const struct net_device *dev,
370 struct can_berr_counter *bec)
372 const struct at91_priv *priv = netdev_priv(dev);
373 u32 reg_ecr = at91_read(priv, AT91_ECR);
375 bec->rxerr = reg_ecr & 0xff;
376 bec->txerr = reg_ecr >> 16;
381 static void at91_chip_start(struct net_device *dev)
383 struct at91_priv *priv = netdev_priv(dev);
386 /* disable interrupts */
387 at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
390 reg_mr = at91_read(priv, AT91_MR);
391 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
393 at91_set_bittiming(dev);
394 at91_setup_mailboxes(dev);
397 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
398 reg_mr = AT91_MR_CANEN | AT91_MR_ABM;
400 reg_mr = AT91_MR_CANEN;
401 at91_write(priv, AT91_MR, reg_mr);
403 priv->can.state = CAN_STATE_ERROR_ACTIVE;
405 /* Enable interrupts */
406 reg_ier = get_irq_mb_rx(priv) | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME;
407 at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
408 at91_write(priv, AT91_IER, reg_ier);
411 static void at91_chip_stop(struct net_device *dev, enum can_state state)
413 struct at91_priv *priv = netdev_priv(dev);
416 /* disable interrupts */
417 at91_write(priv, AT91_IDR, AT91_IRQ_ALL);
419 reg_mr = at91_read(priv, AT91_MR);
420 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN);
422 priv->can.state = state;
425 /* theory of operation:
427 * According to the datasheet priority 0 is the highest priority, 15
428 * is the lowest. If two mailboxes have the same priority level the
429 * message of the mailbox with the lowest number is sent first.
431 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then
432 * the next mailbox with prio 0, and so on, until all mailboxes are
433 * used. Then we start from the beginning with mailbox
434 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1
435 * prio 1. When we reach the last mailbox with prio 15, we have to
436 * stop sending, waiting for all messages to be delivered, then start
437 * again with mailbox AT91_MB_TX_FIRST prio 0.
439 * We use the priv->tx_next as counter for the next transmission
440 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits
441 * encode the mailbox number, the upper 4 bits the mailbox priority:
443 * priv->tx_next = (prio << get_next_prio_shift(priv)) |
444 * (mb - get_mb_tx_first(priv));
447 static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev)
449 struct at91_priv *priv = netdev_priv(dev);
450 struct can_frame *cf = (struct can_frame *)skb->data;
451 unsigned int mb, prio;
452 u32 reg_mid, reg_mcr;
454 if (can_dropped_invalid_skb(dev, skb))
457 mb = get_tx_next_mb(priv);
458 prio = get_tx_next_prio(priv);
460 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) {
461 netif_stop_queue(dev);
463 netdev_err(dev, "BUG! TX buffer full when queue awake!\n");
464 return NETDEV_TX_BUSY;
466 reg_mid = at91_can_id_to_reg_mid(cf->can_id);
467 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) |
468 (cf->len << 16) | AT91_MCR_MTCR;
470 /* disable MB while writing ID (see datasheet) */
471 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED);
472 at91_write(priv, AT91_MID(mb), reg_mid);
473 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio);
475 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0));
476 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4));
478 /* This triggers transmission */
479 at91_write(priv, AT91_MCR(mb), reg_mcr);
481 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
482 can_put_echo_skb(skb, dev, mb - get_mb_tx_first(priv), 0);
484 /* we have to stop the queue and deliver all messages in case
485 * of a prio+mb counter wrap around. This is the case if
486 * tx_next buffer prio and mailbox equals 0.
488 * also stop the queue if next buffer is still in use
492 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) &
494 (priv->tx_next & get_next_mask(priv)) == 0)
495 netif_stop_queue(dev);
497 /* Enable interrupt for this mailbox */
498 at91_write(priv, AT91_IER, 1 << mb);
504 * at91_activate_rx_low - activate lower rx mailboxes
507 * Reenables the lower mailboxes for reception of new CAN messages
509 static inline void at91_activate_rx_low(const struct at91_priv *priv)
511 u32 mask = get_mb_rx_low_mask(priv);
513 at91_write(priv, AT91_TCR, mask);
517 * at91_activate_rx_mb - reactive single rx mailbox
519 * @mb: mailbox to reactivate
521 * Reenables given mailbox for reception of new CAN messages
523 static inline void at91_activate_rx_mb(const struct at91_priv *priv,
528 at91_write(priv, AT91_TCR, mask);
532 * at91_rx_overflow_err - send error frame due to rx overflow
535 static void at91_rx_overflow_err(struct net_device *dev)
537 struct net_device_stats *stats = &dev->stats;
539 struct can_frame *cf;
541 netdev_dbg(dev, "RX buffer overflow\n");
542 stats->rx_over_errors++;
545 skb = alloc_can_err_skb(dev, &cf);
549 cf->can_id |= CAN_ERR_CRTL;
550 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
552 netif_receive_skb(skb);
556 * at91_read_mb - read CAN msg from mailbox (lowlevel impl)
558 * @mb: mailbox number to read from
559 * @cf: can frame where to store message
561 * Reads a CAN message from the given mailbox and stores data into
562 * given can frame. "mb" and "cf" must be valid.
564 static void at91_read_mb(struct net_device *dev, unsigned int mb,
565 struct can_frame *cf)
567 const struct at91_priv *priv = netdev_priv(dev);
568 u32 reg_msr, reg_mid;
570 reg_mid = at91_read(priv, AT91_MID(mb));
571 if (reg_mid & AT91_MID_MIDE)
572 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
574 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK;
576 reg_msr = at91_read(priv, AT91_MSR(mb));
577 cf->len = can_cc_dlc2len((reg_msr >> 16) & 0xf);
579 if (reg_msr & AT91_MSR_MRTR) {
580 cf->can_id |= CAN_RTR_FLAG;
582 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb));
583 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb));
586 /* allow RX of extended frames */
587 at91_write(priv, AT91_MID(mb), AT91_MID_MIDE);
589 if (unlikely(mb == get_mb_rx_last(priv) && reg_msr & AT91_MSR_MMI))
590 at91_rx_overflow_err(dev);
594 * at91_read_msg - read CAN message from mailbox
596 * @mb: mail box to read from
598 * Reads a CAN message from given mailbox, and put into linux network
599 * RX queue, does all housekeeping chores (stats, ...)
601 static void at91_read_msg(struct net_device *dev, unsigned int mb)
603 struct net_device_stats *stats = &dev->stats;
604 struct can_frame *cf;
607 skb = alloc_can_skb(dev, &cf);
608 if (unlikely(!skb)) {
613 at91_read_mb(dev, mb, cf);
616 if (!(cf->can_id & CAN_RTR_FLAG))
617 stats->rx_bytes += cf->len;
619 netif_receive_skb(skb);
623 * at91_poll_rx - read multiple CAN messages from mailboxes
625 * @quota: max number of pkgs we're allowed to receive
627 * Theory of Operation:
629 * About 3/4 of the mailboxes (get_mb_rx_first()...get_mb_rx_last())
630 * on the chip are reserved for RX. We split them into 2 groups. The
631 * lower group ranges from get_mb_rx_first() to get_mb_rx_low_last().
633 * Like it or not, but the chip always saves a received CAN message
634 * into the first free mailbox it finds (starting with the
635 * lowest). This makes it very difficult to read the messages in the
636 * right order from the chip. This is how we work around that problem:
638 * The first message goes into mb nr. 1 and issues an interrupt. All
639 * rx ints are disabled in the interrupt handler and a napi poll is
640 * scheduled. We read the mailbox, but do _not_ re-enable the mb (to
641 * receive another message).
646 * +-+-+-+-+-+-+-+-++-+-+-+-+
647 * | |x|x|x|x|x|x|x|| | | | |
648 * +-+-+-+-+-+-+-+-++-+-+-+-+
649 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail
650 * 0 1 2 3 4 5 6 7 8 9 0 1 / box
654 * unused, due to chip bug
656 * The variable priv->rx_next points to the next mailbox to read a
657 * message from. As long we're in the lower mailboxes we just read the
658 * mailbox but not re-enable it.
660 * With completion of the last of the lower mailboxes, we re-enable the
661 * whole first group, but continue to look for filled mailboxes in the
662 * upper mailboxes. Imagine the second group like overflow mailboxes,
663 * which takes CAN messages if the lower goup is full. While in the
664 * upper group we re-enable the mailbox right after reading it. Giving
665 * the chip more room to store messages.
667 * After finishing we look again in the lower group if we've still
671 static int at91_poll_rx(struct net_device *dev, int quota)
673 struct at91_priv *priv = netdev_priv(dev);
674 u32 reg_sr = at91_read(priv, AT91_SR);
675 const unsigned long *addr = (unsigned long *)®_sr;
679 if (priv->rx_next > get_mb_rx_low_last(priv) &&
680 reg_sr & get_mb_rx_low_mask(priv))
682 "order of incoming frames cannot be guaranteed\n");
685 for (mb = find_next_bit(addr, get_mb_tx_first(priv), priv->rx_next);
686 mb < get_mb_tx_first(priv) && quota > 0;
687 reg_sr = at91_read(priv, AT91_SR),
688 mb = find_next_bit(addr, get_mb_tx_first(priv), ++priv->rx_next)) {
689 at91_read_msg(dev, mb);
691 /* reactivate mailboxes */
692 if (mb == get_mb_rx_low_last(priv))
693 /* all lower mailboxed, if just finished it */
694 at91_activate_rx_low(priv);
695 else if (mb > get_mb_rx_low_last(priv))
696 /* only the mailbox we read */
697 at91_activate_rx_mb(priv, mb);
703 /* upper group completed, look again in lower */
704 if (priv->rx_next > get_mb_rx_low_last(priv) &&
705 mb > get_mb_rx_last(priv)) {
706 priv->rx_next = get_mb_rx_first(priv);
714 static void at91_poll_err_frame(struct net_device *dev,
715 struct can_frame *cf, u32 reg_sr)
717 struct at91_priv *priv = netdev_priv(dev);
720 if (reg_sr & AT91_IRQ_CERR) {
721 netdev_dbg(dev, "CERR irq\n");
722 dev->stats.rx_errors++;
723 priv->can.can_stats.bus_error++;
724 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
728 if (reg_sr & AT91_IRQ_SERR) {
729 netdev_dbg(dev, "SERR irq\n");
730 dev->stats.rx_errors++;
731 priv->can.can_stats.bus_error++;
732 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
733 cf->data[2] |= CAN_ERR_PROT_STUFF;
736 /* Acknowledgement Error */
737 if (reg_sr & AT91_IRQ_AERR) {
738 netdev_dbg(dev, "AERR irq\n");
739 dev->stats.tx_errors++;
740 cf->can_id |= CAN_ERR_ACK;
744 if (reg_sr & AT91_IRQ_FERR) {
745 netdev_dbg(dev, "FERR irq\n");
746 dev->stats.rx_errors++;
747 priv->can.can_stats.bus_error++;
748 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
749 cf->data[2] |= CAN_ERR_PROT_FORM;
753 if (reg_sr & AT91_IRQ_BERR) {
754 netdev_dbg(dev, "BERR irq\n");
755 dev->stats.tx_errors++;
756 priv->can.can_stats.bus_error++;
757 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
758 cf->data[2] |= CAN_ERR_PROT_BIT;
762 static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr)
765 struct can_frame *cf;
770 skb = alloc_can_err_skb(dev, &cf);
774 at91_poll_err_frame(dev, cf, reg_sr);
776 netif_receive_skb(skb);
781 static int at91_poll(struct napi_struct *napi, int quota)
783 struct net_device *dev = napi->dev;
784 const struct at91_priv *priv = netdev_priv(dev);
785 u32 reg_sr = at91_read(priv, AT91_SR);
788 if (reg_sr & get_irq_mb_rx(priv))
789 work_done += at91_poll_rx(dev, quota - work_done);
791 /* The error bits are clear on read,
792 * so use saved value from irq handler.
794 reg_sr |= priv->reg_sr;
795 if (reg_sr & AT91_IRQ_ERR_FRAME)
796 work_done += at91_poll_err(dev, quota - work_done, reg_sr);
798 if (work_done < quota) {
799 /* enable IRQs for frame errors and all mailboxes >= rx_next */
800 u32 reg_ier = AT91_IRQ_ERR_FRAME;
802 reg_ier |= get_irq_mb_rx(priv) & ~AT91_MB_MASK(priv->rx_next);
804 napi_complete_done(napi, work_done);
805 at91_write(priv, AT91_IER, reg_ier);
811 /* theory of operation:
813 * priv->tx_echo holds the number of the oldest can_frame put for
814 * transmission into the hardware, but not yet ACKed by the CAN tx
817 * We iterate from priv->tx_echo to priv->tx_next and check if the
818 * packet has been transmitted, echo it back to the CAN framework. If
819 * we discover a not yet transmitted package, stop looking for more.
822 static void at91_irq_tx(struct net_device *dev, u32 reg_sr)
824 struct at91_priv *priv = netdev_priv(dev);
828 /* masking of reg_sr not needed, already done by at91_irq */
830 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
831 mb = get_tx_echo_mb(priv);
833 /* no event in mailbox? */
834 if (!(reg_sr & (1 << mb)))
837 /* Disable irq for this TX mailbox */
838 at91_write(priv, AT91_IDR, 1 << mb);
840 /* only echo if mailbox signals us a transfer
841 * complete (MSR_MRDY). Otherwise it's a tansfer
842 * abort. "can_bus_off()" takes care about the skbs
843 * parked in the echo queue.
845 reg_msr = at91_read(priv, AT91_MSR(mb));
846 if (likely(reg_msr & AT91_MSR_MRDY &&
847 ~reg_msr & AT91_MSR_MABT)) {
848 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */
849 dev->stats.tx_bytes +=
850 can_get_echo_skb(dev,
851 mb - get_mb_tx_first(priv),
853 dev->stats.tx_packets++;
857 /* restart queue if we don't have a wrap around but restart if
858 * we get a TX int for the last can frame directly before a
861 if ((priv->tx_next & get_next_mask(priv)) != 0 ||
862 (priv->tx_echo & get_next_mask(priv)) == 0)
863 netif_wake_queue(dev);
866 static void at91_irq_err_state(struct net_device *dev,
867 struct can_frame *cf, enum can_state new_state)
869 struct at91_priv *priv = netdev_priv(dev);
870 u32 reg_idr = 0, reg_ier = 0;
871 struct can_berr_counter bec;
873 at91_get_berr_counter(dev, &bec);
875 switch (priv->can.state) {
876 case CAN_STATE_ERROR_ACTIVE:
877 /* from: ERROR_ACTIVE
878 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
879 * => : there was a warning int
881 if (new_state >= CAN_STATE_ERROR_WARNING &&
882 new_state <= CAN_STATE_BUS_OFF) {
883 netdev_dbg(dev, "Error Warning IRQ\n");
884 priv->can.can_stats.error_warning++;
886 cf->can_id |= CAN_ERR_CRTL;
887 cf->data[1] = (bec.txerr > bec.rxerr) ?
888 CAN_ERR_CRTL_TX_WARNING :
889 CAN_ERR_CRTL_RX_WARNING;
892 case CAN_STATE_ERROR_WARNING:
893 /* from: ERROR_ACTIVE, ERROR_WARNING
894 * to : ERROR_PASSIVE, BUS_OFF
895 * => : error passive int
897 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
898 new_state <= CAN_STATE_BUS_OFF) {
899 netdev_dbg(dev, "Error Passive IRQ\n");
900 priv->can.can_stats.error_passive++;
902 cf->can_id |= CAN_ERR_CRTL;
903 cf->data[1] = (bec.txerr > bec.rxerr) ?
904 CAN_ERR_CRTL_TX_PASSIVE :
905 CAN_ERR_CRTL_RX_PASSIVE;
908 case CAN_STATE_BUS_OFF:
910 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE
912 if (new_state <= CAN_STATE_ERROR_PASSIVE) {
913 cf->can_id |= CAN_ERR_RESTARTED;
915 netdev_dbg(dev, "restarted\n");
916 priv->can.can_stats.restarts++;
918 netif_carrier_on(dev);
919 netif_wake_queue(dev);
926 /* process state changes depending on the new state */
928 case CAN_STATE_ERROR_ACTIVE:
929 /* actually we want to enable AT91_IRQ_WARN here, but
930 * it screws up the system under certain
931 * circumstances. so just enable AT91_IRQ_ERRP, thus
934 netdev_dbg(dev, "Error Active\n");
935 cf->can_id |= CAN_ERR_PROT;
936 cf->data[2] = CAN_ERR_PROT_ACTIVE;
938 case CAN_STATE_ERROR_WARNING:
939 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF;
940 reg_ier = AT91_IRQ_ERRP;
942 case CAN_STATE_ERROR_PASSIVE:
943 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP;
944 reg_ier = AT91_IRQ_BOFF;
946 case CAN_STATE_BUS_OFF:
947 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP |
948 AT91_IRQ_WARN | AT91_IRQ_BOFF;
951 cf->can_id |= CAN_ERR_BUSOFF;
953 netdev_dbg(dev, "bus-off\n");
954 netif_carrier_off(dev);
955 priv->can.can_stats.bus_off++;
957 /* turn off chip, if restart is disabled */
958 if (!priv->can.restart_ms) {
959 at91_chip_stop(dev, CAN_STATE_BUS_OFF);
967 at91_write(priv, AT91_IDR, reg_idr);
968 at91_write(priv, AT91_IER, reg_ier);
971 static int at91_get_state_by_bec(const struct net_device *dev,
972 enum can_state *state)
974 struct can_berr_counter bec;
977 err = at91_get_berr_counter(dev, &bec);
981 if (bec.txerr < 96 && bec.rxerr < 96)
982 *state = CAN_STATE_ERROR_ACTIVE;
983 else if (bec.txerr < 128 && bec.rxerr < 128)
984 *state = CAN_STATE_ERROR_WARNING;
985 else if (bec.txerr < 256 && bec.rxerr < 256)
986 *state = CAN_STATE_ERROR_PASSIVE;
988 *state = CAN_STATE_BUS_OFF;
993 static void at91_irq_err(struct net_device *dev)
995 struct at91_priv *priv = netdev_priv(dev);
997 struct can_frame *cf;
998 enum can_state new_state;
1002 if (at91_is_sam9263(priv)) {
1003 reg_sr = at91_read(priv, AT91_SR);
1005 /* we need to look at the unmasked reg_sr */
1006 if (unlikely(reg_sr & AT91_IRQ_BOFF)) {
1007 new_state = CAN_STATE_BUS_OFF;
1008 } else if (unlikely(reg_sr & AT91_IRQ_ERRP)) {
1009 new_state = CAN_STATE_ERROR_PASSIVE;
1010 } else if (unlikely(reg_sr & AT91_IRQ_WARN)) {
1011 new_state = CAN_STATE_ERROR_WARNING;
1012 } else if (likely(reg_sr & AT91_IRQ_ERRA)) {
1013 new_state = CAN_STATE_ERROR_ACTIVE;
1015 netdev_err(dev, "BUG! hardware in undefined state\n");
1019 err = at91_get_state_by_bec(dev, &new_state);
1024 /* state hasn't changed */
1025 if (likely(new_state == priv->can.state))
1028 skb = alloc_can_err_skb(dev, &cf);
1032 at91_irq_err_state(dev, cf, new_state);
1036 priv->can.state = new_state;
1039 /* interrupt handler
1041 static irqreturn_t at91_irq(int irq, void *dev_id)
1043 struct net_device *dev = dev_id;
1044 struct at91_priv *priv = netdev_priv(dev);
1045 irqreturn_t handled = IRQ_NONE;
1046 u32 reg_sr, reg_imr;
1048 reg_sr = at91_read(priv, AT91_SR);
1049 reg_imr = at91_read(priv, AT91_IMR);
1051 /* Ignore masked interrupts */
1056 handled = IRQ_HANDLED;
1058 /* Receive or error interrupt? -> napi */
1059 if (reg_sr & (get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME)) {
1060 /* The error bits are clear on read,
1061 * save for later use.
1063 priv->reg_sr = reg_sr;
1064 at91_write(priv, AT91_IDR,
1065 get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME);
1066 napi_schedule(&priv->napi);
1069 /* Transmission complete interrupt */
1070 if (reg_sr & get_irq_mb_tx(priv))
1071 at91_irq_tx(dev, reg_sr);
1079 static int at91_open(struct net_device *dev)
1081 struct at91_priv *priv = netdev_priv(dev);
1084 err = clk_prepare_enable(priv->clk);
1088 /* check or determine and set bittime */
1089 err = open_candev(dev);
1093 /* register interrupt handler */
1094 if (request_irq(dev->irq, at91_irq, IRQF_SHARED,
1100 /* start chip and queuing */
1101 at91_chip_start(dev);
1102 napi_enable(&priv->napi);
1103 netif_start_queue(dev);
1110 clk_disable_unprepare(priv->clk);
1115 /* stop CAN bus activity
1117 static int at91_close(struct net_device *dev)
1119 struct at91_priv *priv = netdev_priv(dev);
1121 netif_stop_queue(dev);
1122 napi_disable(&priv->napi);
1123 at91_chip_stop(dev, CAN_STATE_STOPPED);
1125 free_irq(dev->irq, dev);
1126 clk_disable_unprepare(priv->clk);
1133 static int at91_set_mode(struct net_device *dev, enum can_mode mode)
1136 case CAN_MODE_START:
1137 at91_chip_start(dev);
1138 netif_wake_queue(dev);
1148 static const struct net_device_ops at91_netdev_ops = {
1149 .ndo_open = at91_open,
1150 .ndo_stop = at91_close,
1151 .ndo_start_xmit = at91_start_xmit,
1152 .ndo_change_mtu = can_change_mtu,
1155 static ssize_t mb0_id_show(struct device *dev,
1156 struct device_attribute *attr, char *buf)
1158 struct at91_priv *priv = netdev_priv(to_net_dev(dev));
1160 if (priv->mb0_id & CAN_EFF_FLAG)
1161 return sysfs_emit(buf, "0x%08x\n", priv->mb0_id);
1163 return sysfs_emit(buf, "0x%03x\n", priv->mb0_id);
1166 static ssize_t mb0_id_store(struct device *dev,
1167 struct device_attribute *attr,
1168 const char *buf, size_t count)
1170 struct net_device *ndev = to_net_dev(dev);
1171 struct at91_priv *priv = netdev_priv(ndev);
1172 unsigned long can_id;
1178 if (ndev->flags & IFF_UP) {
1183 err = kstrtoul(buf, 0, &can_id);
1189 if (can_id & CAN_EFF_FLAG)
1190 can_id &= CAN_EFF_MASK | CAN_EFF_FLAG;
1192 can_id &= CAN_SFF_MASK;
1194 priv->mb0_id = can_id;
1202 static DEVICE_ATTR_RW(mb0_id);
1204 static struct attribute *at91_sysfs_attrs[] = {
1205 &dev_attr_mb0_id.attr,
1209 static const struct attribute_group at91_sysfs_attr_group = {
1210 .attrs = at91_sysfs_attrs,
1213 #if defined(CONFIG_OF)
1214 static const struct of_device_id at91_can_dt_ids[] = {
1216 .compatible = "atmel,at91sam9x5-can",
1217 .data = &at91_at91sam9x5_data,
1219 .compatible = "atmel,at91sam9263-can",
1220 .data = &at91_at91sam9263_data,
1225 MODULE_DEVICE_TABLE(of, at91_can_dt_ids);
1228 static const struct at91_devtype_data *at91_can_get_driver_data(struct platform_device *pdev)
1230 if (pdev->dev.of_node) {
1231 const struct of_device_id *match;
1233 match = of_match_node(at91_can_dt_ids, pdev->dev.of_node);
1235 dev_err(&pdev->dev, "no matching node found in dtb\n");
1238 return (const struct at91_devtype_data *)match->data;
1240 return (const struct at91_devtype_data *)
1241 platform_get_device_id(pdev)->driver_data;
1244 static int at91_can_probe(struct platform_device *pdev)
1246 const struct at91_devtype_data *devtype_data;
1247 struct net_device *dev;
1248 struct at91_priv *priv;
1249 struct resource *res;
1254 devtype_data = at91_can_get_driver_data(pdev);
1255 if (!devtype_data) {
1256 dev_err(&pdev->dev, "no driver data\n");
1261 clk = clk_get(&pdev->dev, "can_clk");
1263 dev_err(&pdev->dev, "no clock defined\n");
1268 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1269 irq = platform_get_irq(pdev, 0);
1270 if (!res || irq <= 0) {
1275 if (!request_mem_region(res->start,
1282 addr = ioremap(res->start, resource_size(res));
1288 dev = alloc_candev(sizeof(struct at91_priv),
1289 1 << devtype_data->tx_shift);
1295 dev->netdev_ops = &at91_netdev_ops;
1297 dev->flags |= IFF_ECHO;
1299 priv = netdev_priv(dev);
1300 priv->can.clock.freq = clk_get_rate(clk);
1301 priv->can.bittiming_const = &at91_bittiming_const;
1302 priv->can.do_set_mode = at91_set_mode;
1303 priv->can.do_get_berr_counter = at91_get_berr_counter;
1304 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1305 CAN_CTRLMODE_LISTENONLY;
1306 priv->reg_base = addr;
1307 priv->devtype_data = *devtype_data;
1309 priv->pdata = dev_get_platdata(&pdev->dev);
1310 priv->mb0_id = 0x7ff;
1312 netif_napi_add_weight(dev, &priv->napi, at91_poll, get_mb_rx_num(priv));
1314 if (at91_is_sam9263(priv))
1315 dev->sysfs_groups[0] = &at91_sysfs_attr_group;
1317 platform_set_drvdata(pdev, dev);
1318 SET_NETDEV_DEV(dev, &pdev->dev);
1320 err = register_candev(dev);
1322 dev_err(&pdev->dev, "registering netdev failed\n");
1326 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1327 priv->reg_base, dev->irq);
1336 release_mem_region(res->start, resource_size(res));
1343 static int at91_can_remove(struct platform_device *pdev)
1345 struct net_device *dev = platform_get_drvdata(pdev);
1346 struct at91_priv *priv = netdev_priv(dev);
1347 struct resource *res;
1349 unregister_netdev(dev);
1351 iounmap(priv->reg_base);
1353 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1354 release_mem_region(res->start, resource_size(res));
1363 static const struct platform_device_id at91_can_id_table[] = {
1365 .name = "at91sam9x5_can",
1366 .driver_data = (kernel_ulong_t)&at91_at91sam9x5_data,
1369 .driver_data = (kernel_ulong_t)&at91_at91sam9263_data,
1374 MODULE_DEVICE_TABLE(platform, at91_can_id_table);
1376 static struct platform_driver at91_can_driver = {
1377 .probe = at91_can_probe,
1378 .remove = at91_can_remove,
1380 .name = KBUILD_MODNAME,
1381 .of_match_table = of_match_ptr(at91_can_dt_ids),
1383 .id_table = at91_can_id_table,
1386 module_platform_driver(at91_can_driver);
1388 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
1389 MODULE_LICENSE("GPL v2");
1390 MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver");