1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
7 #include <linux/mod_devicetable.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
12 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
18 #include "clk-regmap-divider.h"
19 #include "clk-regmap-mux.h"
20 #include "clk-regmap.h"
34 P_CAM_CC_PLL0_OUT_EVEN,
35 P_CAM_CC_PLL0_OUT_MAIN,
36 P_CAM_CC_PLL0_OUT_ODD,
37 P_CAM_CC_PLL1_OUT_EVEN,
38 P_CAM_CC_PLL2_OUT_EVEN,
39 P_CAM_CC_PLL2_OUT_MAIN,
40 P_CAM_CC_PLL3_OUT_EVEN,
41 P_CAM_CC_PLL4_OUT_EVEN,
42 P_CAM_CC_PLL5_OUT_EVEN,
43 P_CAM_CC_PLL6_OUT_EVEN,
44 P_CAM_CC_PLL7_OUT_EVEN,
45 P_CAM_CC_PLL8_OUT_EVEN,
49 static const struct pll_vco lucid_evo_vco[] = {
50 { 249600000, 2000000000, 0 },
53 static const struct pll_vco rivian_evo_vco[] = {
54 { 864000000, 1056000000, 0 },
57 static const struct clk_parent_data pll_parent_data_tcxo = { .index = DT_BI_TCXO };
59 static const struct alpha_pll_config cam_cc_pll0_config = {
62 .config_ctl_val = 0x20485699,
63 .config_ctl_hi_val = 0x00182261,
64 .config_ctl_hi1_val = 0x32aa299c,
65 .user_ctl_val = 0x00008400,
66 .user_ctl_hi_val = 0x00000805,
69 static struct clk_alpha_pll cam_cc_pll0 = {
71 .vco_table = lucid_evo_vco,
72 .num_vco = ARRAY_SIZE(lucid_evo_vco),
73 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
75 .hw.init = &(const struct clk_init_data) {
76 .name = "cam_cc_pll0",
77 .parent_data = &pll_parent_data_tcxo,
79 .ops = &clk_alpha_pll_lucid_evo_ops,
84 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
89 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
92 .post_div_table = post_div_table_cam_cc_pll0_out_even,
93 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
95 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
96 .clkr.hw.init = &(const struct clk_init_data) {
97 .name = "cam_cc_pll0_out_even",
98 .parent_hws = (const struct clk_hw*[]) {
102 .flags = CLK_SET_RATE_PARENT,
103 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
107 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
112 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
114 .post_div_shift = 14,
115 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
116 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
118 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
119 .clkr.hw.init = &(const struct clk_init_data) {
120 .name = "cam_cc_pll0_out_odd",
121 .parent_hws = (const struct clk_hw*[]) {
122 &cam_cc_pll0.clkr.hw,
125 .flags = CLK_SET_RATE_PARENT,
126 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
130 static const struct alpha_pll_config cam_cc_pll1_config = {
133 .config_ctl_val = 0x20485699,
134 .config_ctl_hi_val = 0x00182261,
135 .config_ctl_hi1_val = 0x32aa299c,
136 .user_ctl_val = 0x00000400,
137 .user_ctl_hi_val = 0x00000805,
140 static struct clk_alpha_pll cam_cc_pll1 = {
142 .vco_table = lucid_evo_vco,
143 .num_vco = ARRAY_SIZE(lucid_evo_vco),
144 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
146 .hw.init = &(const struct clk_init_data) {
147 .name = "cam_cc_pll1",
148 .parent_data = &pll_parent_data_tcxo,
150 .ops = &clk_alpha_pll_lucid_evo_ops,
155 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
160 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
162 .post_div_shift = 10,
163 .post_div_table = post_div_table_cam_cc_pll1_out_even,
164 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
166 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
167 .clkr.hw.init = &(const struct clk_init_data) {
168 .name = "cam_cc_pll1_out_even",
169 .parent_hws = (const struct clk_hw*[]) {
170 &cam_cc_pll1.clkr.hw,
173 .flags = CLK_SET_RATE_PARENT,
174 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
178 static const struct alpha_pll_config cam_cc_pll2_config = {
181 .config_ctl_val = 0x90008820,
182 .config_ctl_hi_val = 0x00890263,
183 .config_ctl_hi1_val = 0x00000217,
186 static struct clk_alpha_pll cam_cc_pll2 = {
188 .vco_table = rivian_evo_vco,
189 .num_vco = ARRAY_SIZE(rivian_evo_vco),
190 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
192 .hw.init = &(const struct clk_init_data) {
193 .name = "cam_cc_pll2",
194 .parent_data = &pll_parent_data_tcxo,
196 .ops = &clk_alpha_pll_rivian_evo_ops,
201 static const struct alpha_pll_config cam_cc_pll3_config = {
204 .config_ctl_val = 0x20485699,
205 .config_ctl_hi_val = 0x00182261,
206 .config_ctl_hi1_val = 0x32aa299c,
207 .user_ctl_val = 0x00000400,
208 .user_ctl_hi_val = 0x00000805,
211 static struct clk_alpha_pll cam_cc_pll3 = {
213 .vco_table = lucid_evo_vco,
214 .num_vco = ARRAY_SIZE(lucid_evo_vco),
215 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
217 .hw.init = &(const struct clk_init_data) {
218 .name = "cam_cc_pll3",
219 .parent_data = &pll_parent_data_tcxo,
221 .ops = &clk_alpha_pll_lucid_evo_ops,
226 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
231 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
233 .post_div_shift = 10,
234 .post_div_table = post_div_table_cam_cc_pll3_out_even,
235 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
237 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
238 .clkr.hw.init = &(const struct clk_init_data) {
239 .name = "cam_cc_pll3_out_even",
240 .parent_hws = (const struct clk_hw*[]) {
241 &cam_cc_pll3.clkr.hw,
244 .flags = CLK_SET_RATE_PARENT,
245 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
249 static const struct alpha_pll_config cam_cc_pll4_config = {
252 .config_ctl_val = 0x20485699,
253 .config_ctl_hi_val = 0x00182261,
254 .config_ctl_hi1_val = 0x32aa299c,
255 .user_ctl_val = 0x00000400,
256 .user_ctl_hi_val = 0x00000805,
259 static struct clk_alpha_pll cam_cc_pll4 = {
261 .vco_table = lucid_evo_vco,
262 .num_vco = ARRAY_SIZE(lucid_evo_vco),
263 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
265 .hw.init = &(const struct clk_init_data) {
266 .name = "cam_cc_pll4",
267 .parent_data = &pll_parent_data_tcxo,
269 .ops = &clk_alpha_pll_lucid_evo_ops,
274 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
279 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
281 .post_div_shift = 10,
282 .post_div_table = post_div_table_cam_cc_pll4_out_even,
283 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
285 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
286 .clkr.hw.init = &(const struct clk_init_data) {
287 .name = "cam_cc_pll4_out_even",
288 .parent_hws = (const struct clk_hw*[]) {
289 &cam_cc_pll4.clkr.hw,
292 .flags = CLK_SET_RATE_PARENT,
293 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
297 static const struct alpha_pll_config cam_cc_pll5_config = {
300 .config_ctl_val = 0x20485699,
301 .config_ctl_hi_val = 0x00182261,
302 .config_ctl_hi1_val = 0x32aa299c,
303 .user_ctl_val = 0x00000400,
304 .user_ctl_hi_val = 0x00000805,
307 static struct clk_alpha_pll cam_cc_pll5 = {
309 .vco_table = lucid_evo_vco,
310 .num_vco = ARRAY_SIZE(lucid_evo_vco),
311 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
313 .hw.init = &(const struct clk_init_data) {
314 .name = "cam_cc_pll5",
315 .parent_data = &pll_parent_data_tcxo,
317 .ops = &clk_alpha_pll_lucid_evo_ops,
322 static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
327 static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
329 .post_div_shift = 10,
330 .post_div_table = post_div_table_cam_cc_pll5_out_even,
331 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even),
333 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
334 .clkr.hw.init = &(const struct clk_init_data) {
335 .name = "cam_cc_pll5_out_even",
336 .parent_hws = (const struct clk_hw*[]) {
337 &cam_cc_pll5.clkr.hw,
340 .flags = CLK_SET_RATE_PARENT,
341 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
345 static const struct alpha_pll_config cam_cc_pll6_config = {
348 .config_ctl_val = 0x20485699,
349 .config_ctl_hi_val = 0x00182261,
350 .config_ctl_hi1_val = 0x32aa299c,
351 .user_ctl_val = 0x00000400,
352 .user_ctl_hi_val = 0x00000805,
355 static struct clk_alpha_pll cam_cc_pll6 = {
357 .vco_table = lucid_evo_vco,
358 .num_vco = ARRAY_SIZE(lucid_evo_vco),
359 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
361 .hw.init = &(const struct clk_init_data) {
362 .name = "cam_cc_pll6",
363 .parent_data = &pll_parent_data_tcxo,
365 .ops = &clk_alpha_pll_lucid_evo_ops,
370 static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = {
375 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
377 .post_div_shift = 10,
378 .post_div_table = post_div_table_cam_cc_pll6_out_even,
379 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even),
381 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
382 .clkr.hw.init = &(const struct clk_init_data) {
383 .name = "cam_cc_pll6_out_even",
384 .parent_hws = (const struct clk_hw*[]) {
385 &cam_cc_pll6.clkr.hw,
388 .flags = CLK_SET_RATE_PARENT,
389 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
393 static const struct alpha_pll_config cam_cc_pll7_config = {
396 .config_ctl_val = 0x20485699,
397 .config_ctl_hi_val = 0x00182261,
398 .config_ctl_hi1_val = 0x32aa299c,
399 .user_ctl_val = 0x00000400,
400 .user_ctl_hi_val = 0x00000805,
403 static struct clk_alpha_pll cam_cc_pll7 = {
405 .vco_table = lucid_evo_vco,
406 .num_vco = ARRAY_SIZE(lucid_evo_vco),
407 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
409 .hw.init = &(const struct clk_init_data) {
410 .name = "cam_cc_pll7",
411 .parent_data = &pll_parent_data_tcxo,
413 .ops = &clk_alpha_pll_lucid_evo_ops,
418 static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = {
423 static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
425 .post_div_shift = 10,
426 .post_div_table = post_div_table_cam_cc_pll7_out_even,
427 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even),
429 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
430 .clkr.hw.init = &(const struct clk_init_data) {
431 .name = "cam_cc_pll7_out_even",
432 .parent_hws = (const struct clk_hw*[]) {
433 &cam_cc_pll7.clkr.hw,
436 .flags = CLK_SET_RATE_PARENT,
437 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
441 static const struct alpha_pll_config cam_cc_pll8_config = {
444 .config_ctl_val = 0x20485699,
445 .config_ctl_hi_val = 0x00182261,
446 .config_ctl_hi1_val = 0x32aa299c,
447 .user_ctl_val = 0x00000400,
448 .user_ctl_hi_val = 0x00000805,
451 static struct clk_alpha_pll cam_cc_pll8 = {
453 .vco_table = lucid_evo_vco,
454 .num_vco = ARRAY_SIZE(lucid_evo_vco),
455 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
457 .hw.init = &(const struct clk_init_data) {
458 .name = "cam_cc_pll8",
459 .parent_data = &pll_parent_data_tcxo,
461 .ops = &clk_alpha_pll_lucid_evo_ops,
466 static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = {
471 static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = {
473 .post_div_shift = 10,
474 .post_div_table = post_div_table_cam_cc_pll8_out_even,
475 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even),
477 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
478 .clkr.hw.init = &(const struct clk_init_data) {
479 .name = "cam_cc_pll8_out_even",
480 .parent_hws = (const struct clk_hw*[]) {
481 &cam_cc_pll8.clkr.hw,
484 .flags = CLK_SET_RATE_PARENT,
485 .ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
489 static const struct parent_map cam_cc_parent_map_0[] = {
491 { P_CAM_CC_PLL0_OUT_MAIN, 1 },
492 { P_CAM_CC_PLL0_OUT_EVEN, 2 },
493 { P_CAM_CC_PLL0_OUT_ODD, 3 },
494 { P_CAM_CC_PLL8_OUT_EVEN, 5 },
497 static const struct clk_parent_data cam_cc_parent_data_0[] = {
498 { .index = DT_BI_TCXO },
499 { .hw = &cam_cc_pll0.clkr.hw },
500 { .hw = &cam_cc_pll0_out_even.clkr.hw },
501 { .hw = &cam_cc_pll0_out_odd.clkr.hw },
502 { .hw = &cam_cc_pll8_out_even.clkr.hw },
505 static const struct parent_map cam_cc_parent_map_1[] = {
507 { P_CAM_CC_PLL2_OUT_EVEN, 3 },
508 { P_CAM_CC_PLL2_OUT_MAIN, 5 },
511 static const struct clk_parent_data cam_cc_parent_data_1[] = {
512 { .index = DT_BI_TCXO },
513 { .hw = &cam_cc_pll2.clkr.hw },
514 { .hw = &cam_cc_pll2.clkr.hw },
517 static const struct parent_map cam_cc_parent_map_2[] = {
519 { P_CAM_CC_PLL3_OUT_EVEN, 6 },
522 static const struct clk_parent_data cam_cc_parent_data_2[] = {
523 { .index = DT_BI_TCXO },
524 { .hw = &cam_cc_pll3_out_even.clkr.hw },
527 static const struct parent_map cam_cc_parent_map_3[] = {
529 { P_CAM_CC_PLL4_OUT_EVEN, 6 },
532 static const struct clk_parent_data cam_cc_parent_data_3[] = {
533 { .index = DT_BI_TCXO },
534 { .hw = &cam_cc_pll4_out_even.clkr.hw },
537 static const struct parent_map cam_cc_parent_map_4[] = {
539 { P_CAM_CC_PLL5_OUT_EVEN, 6 },
542 static const struct clk_parent_data cam_cc_parent_data_4[] = {
543 { .index = DT_BI_TCXO },
544 { .hw = &cam_cc_pll5_out_even.clkr.hw },
547 static const struct parent_map cam_cc_parent_map_5[] = {
549 { P_CAM_CC_PLL1_OUT_EVEN, 4 },
552 static const struct clk_parent_data cam_cc_parent_data_5[] = {
553 { .index = DT_BI_TCXO },
554 { .hw = &cam_cc_pll1_out_even.clkr.hw },
557 static const struct parent_map cam_cc_parent_map_6[] = {
559 { P_CAM_CC_PLL6_OUT_EVEN, 6 },
562 static const struct clk_parent_data cam_cc_parent_data_6[] = {
563 { .index = DT_BI_TCXO },
564 { .hw = &cam_cc_pll6_out_even.clkr.hw },
567 static const struct parent_map cam_cc_parent_map_7[] = {
569 { P_CAM_CC_PLL7_OUT_EVEN, 6 },
572 static const struct clk_parent_data cam_cc_parent_data_7[] = {
573 { .index = DT_BI_TCXO },
574 { .hw = &cam_cc_pll7_out_even.clkr.hw },
577 static const struct parent_map cam_cc_parent_map_8[] = {
581 static const struct clk_parent_data cam_cc_parent_data_8[] = {
582 { .index = DT_SLEEP_CLK },
585 static const struct parent_map cam_cc_parent_map_9[] = {
589 static const struct clk_parent_data cam_cc_parent_data_9_ao[] = {
590 { .index = DT_BI_TCXO_AO, .name = "bi_tcxo_ao" },
593 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
594 F(19200000, P_BI_TCXO, 1, 0, 0),
595 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
596 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
597 F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
598 F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
602 static struct clk_rcg2 cam_cc_bps_clk_src = {
606 .parent_map = cam_cc_parent_map_0,
607 .freq_tbl = ftbl_cam_cc_bps_clk_src,
608 .clkr.hw.init = &(const struct clk_init_data) {
609 .name = "cam_cc_bps_clk_src",
610 .parent_data = cam_cc_parent_data_0,
611 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
612 .flags = CLK_SET_RATE_PARENT,
613 .ops = &clk_rcg2_ops,
617 static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
618 F(19200000, P_BI_TCXO, 1, 0, 0),
619 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
620 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
624 static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
628 .parent_map = cam_cc_parent_map_0,
629 .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
630 .clkr.hw.init = &(const struct clk_init_data) {
631 .name = "cam_cc_camnoc_axi_clk_src",
632 .parent_data = cam_cc_parent_data_0,
633 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
634 .flags = CLK_SET_RATE_PARENT,
635 .ops = &clk_rcg2_ops,
639 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
640 F(19200000, P_BI_TCXO, 1, 0, 0),
641 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
645 static struct clk_rcg2 cam_cc_cci_0_clk_src = {
649 .parent_map = cam_cc_parent_map_0,
650 .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
651 .clkr.hw.init = &(const struct clk_init_data) {
652 .name = "cam_cc_cci_0_clk_src",
653 .parent_data = cam_cc_parent_data_0,
654 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
655 .flags = CLK_SET_RATE_PARENT,
656 .ops = &clk_rcg2_ops,
660 static struct clk_rcg2 cam_cc_cci_1_clk_src = {
664 .parent_map = cam_cc_parent_map_0,
665 .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
666 .clkr.hw.init = &(const struct clk_init_data) {
667 .name = "cam_cc_cci_1_clk_src",
668 .parent_data = cam_cc_parent_data_0,
669 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
670 .flags = CLK_SET_RATE_PARENT,
671 .ops = &clk_rcg2_ops,
675 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
676 F(19200000, P_BI_TCXO, 1, 0, 0),
677 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
678 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
682 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
686 .parent_map = cam_cc_parent_map_0,
687 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
688 .clkr.hw.init = &(const struct clk_init_data) {
689 .name = "cam_cc_cphy_rx_clk_src",
690 .parent_data = cam_cc_parent_data_0,
691 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
692 .flags = CLK_SET_RATE_PARENT,
693 .ops = &clk_rcg2_ops,
697 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
698 F(19200000, P_BI_TCXO, 1, 0, 0),
699 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
703 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
707 .parent_map = cam_cc_parent_map_0,
708 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
709 .clkr.hw.init = &(const struct clk_init_data) {
710 .name = "cam_cc_csi0phytimer_clk_src",
711 .parent_data = cam_cc_parent_data_0,
712 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
713 .flags = CLK_SET_RATE_PARENT,
714 .ops = &clk_rcg2_ops,
718 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
722 .parent_map = cam_cc_parent_map_0,
723 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
724 .clkr.hw.init = &(const struct clk_init_data) {
725 .name = "cam_cc_csi1phytimer_clk_src",
726 .parent_data = cam_cc_parent_data_0,
727 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
728 .flags = CLK_SET_RATE_PARENT,
729 .ops = &clk_rcg2_ops,
733 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
737 .parent_map = cam_cc_parent_map_0,
738 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
739 .clkr.hw.init = &(const struct clk_init_data) {
740 .name = "cam_cc_csi2phytimer_clk_src",
741 .parent_data = cam_cc_parent_data_0,
742 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
743 .flags = CLK_SET_RATE_PARENT,
744 .ops = &clk_rcg2_ops,
748 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
752 .parent_map = cam_cc_parent_map_0,
753 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
754 .clkr.hw.init = &(const struct clk_init_data) {
755 .name = "cam_cc_csi3phytimer_clk_src",
756 .parent_data = cam_cc_parent_data_0,
757 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
758 .flags = CLK_SET_RATE_PARENT,
759 .ops = &clk_rcg2_ops,
763 static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
767 .parent_map = cam_cc_parent_map_0,
768 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
769 .clkr.hw.init = &(const struct clk_init_data) {
770 .name = "cam_cc_csi4phytimer_clk_src",
771 .parent_data = cam_cc_parent_data_0,
772 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
773 .flags = CLK_SET_RATE_PARENT,
774 .ops = &clk_rcg2_ops,
778 static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = {
782 .parent_map = cam_cc_parent_map_0,
783 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
784 .clkr.hw.init = &(const struct clk_init_data) {
785 .name = "cam_cc_csi5phytimer_clk_src",
786 .parent_data = cam_cc_parent_data_0,
787 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
788 .flags = CLK_SET_RATE_PARENT,
789 .ops = &clk_rcg2_ops,
793 static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = {
794 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
795 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
799 static struct clk_rcg2 cam_cc_csid_clk_src = {
803 .parent_map = cam_cc_parent_map_0,
804 .freq_tbl = ftbl_cam_cc_csid_clk_src,
805 .clkr.hw.init = &(const struct clk_init_data) {
806 .name = "cam_cc_csid_clk_src",
807 .parent_data = cam_cc_parent_data_0,
808 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
809 .flags = CLK_SET_RATE_PARENT,
810 .ops = &clk_rcg2_ops,
814 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
815 F(19200000, P_BI_TCXO, 1, 0, 0),
816 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
817 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
818 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
819 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
823 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
827 .parent_map = cam_cc_parent_map_0,
828 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
829 .clkr.hw.init = &(const struct clk_init_data) {
830 .name = "cam_cc_fast_ahb_clk_src",
831 .parent_data = cam_cc_parent_data_0,
832 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
833 .flags = CLK_SET_RATE_PARENT,
834 .ops = &clk_rcg2_ops,
838 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
839 F(19200000, P_BI_TCXO, 1, 0, 0),
840 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
841 F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
842 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
846 static struct clk_rcg2 cam_cc_icp_clk_src = {
850 .parent_map = cam_cc_parent_map_0,
851 .freq_tbl = ftbl_cam_cc_icp_clk_src,
852 .clkr.hw.init = &(const struct clk_init_data) {
853 .name = "cam_cc_icp_clk_src",
854 .parent_data = cam_cc_parent_data_0,
855 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
856 .flags = CLK_SET_RATE_PARENT,
857 .ops = &clk_rcg2_ops,
861 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
862 F(19200000, P_BI_TCXO, 1, 0, 0),
863 F(432000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
864 F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
865 F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
866 F(727000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
870 static struct clk_rcg2 cam_cc_ife_0_clk_src = {
874 .parent_map = cam_cc_parent_map_2,
875 .freq_tbl = ftbl_cam_cc_ife_0_clk_src,
876 .clkr.hw.init = &(const struct clk_init_data) {
877 .name = "cam_cc_ife_0_clk_src",
878 .parent_data = cam_cc_parent_data_2,
879 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
880 .flags = CLK_SET_RATE_PARENT,
881 .ops = &clk_rcg2_ops,
885 static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
886 F(19200000, P_BI_TCXO, 1, 0, 0),
887 F(432000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
888 F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
889 F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
890 F(727000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
894 static struct clk_rcg2 cam_cc_ife_1_clk_src = {
898 .parent_map = cam_cc_parent_map_3,
899 .freq_tbl = ftbl_cam_cc_ife_1_clk_src,
900 .clkr.hw.init = &(const struct clk_init_data) {
901 .name = "cam_cc_ife_1_clk_src",
902 .parent_data = cam_cc_parent_data_3,
903 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
904 .flags = CLK_SET_RATE_PARENT,
905 .ops = &clk_rcg2_ops,
909 static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = {
910 F(432000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
911 F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
912 F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
913 F(727000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
917 static struct clk_rcg2 cam_cc_ife_2_clk_src = {
921 .parent_map = cam_cc_parent_map_4,
922 .freq_tbl = ftbl_cam_cc_ife_2_clk_src,
923 .clkr.hw.init = &(const struct clk_init_data) {
924 .name = "cam_cc_ife_2_clk_src",
925 .parent_data = cam_cc_parent_data_4,
926 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
927 .flags = CLK_SET_RATE_PARENT,
928 .ops = &clk_rcg2_ops,
932 static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = {
933 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
934 F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
938 static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
942 .parent_map = cam_cc_parent_map_0,
943 .freq_tbl = ftbl_cam_cc_ife_lite_clk_src,
944 .clkr.hw.init = &(const struct clk_init_data) {
945 .name = "cam_cc_ife_lite_clk_src",
946 .parent_data = cam_cc_parent_data_0,
947 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
948 .flags = CLK_SET_RATE_PARENT,
949 .ops = &clk_rcg2_ops,
953 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
957 .parent_map = cam_cc_parent_map_0,
958 .freq_tbl = ftbl_cam_cc_ife_lite_clk_src,
959 .clkr.hw.init = &(const struct clk_init_data) {
960 .name = "cam_cc_ife_lite_csid_clk_src",
961 .parent_data = cam_cc_parent_data_0,
962 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
963 .flags = CLK_SET_RATE_PARENT,
964 .ops = &clk_rcg2_ops,
968 static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = {
969 F(364000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
970 F(500000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
971 F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
972 F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
976 static struct clk_rcg2 cam_cc_ipe_nps_clk_src = {
980 .parent_map = cam_cc_parent_map_5,
981 .freq_tbl = ftbl_cam_cc_ipe_nps_clk_src,
982 .clkr.hw.init = &(const struct clk_init_data) {
983 .name = "cam_cc_ipe_nps_clk_src",
984 .parent_data = cam_cc_parent_data_5,
985 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
986 .flags = CLK_SET_RATE_PARENT,
987 .ops = &clk_rcg2_ops,
991 static struct clk_rcg2 cam_cc_jpeg_clk_src = {
995 .parent_map = cam_cc_parent_map_0,
996 .freq_tbl = ftbl_cam_cc_bps_clk_src,
997 .clkr.hw.init = &(const struct clk_init_data) {
998 .name = "cam_cc_jpeg_clk_src",
999 .parent_data = cam_cc_parent_data_0,
1000 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1001 .flags = CLK_SET_RATE_PARENT,
1002 .ops = &clk_rcg2_ops,
1006 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
1007 F(19200000, P_BI_TCXO, 1, 0, 0),
1008 F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4),
1009 F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0),
1013 static struct clk_rcg2 cam_cc_mclk0_clk_src = {
1014 .cmd_rcgr = 0x15000,
1017 .parent_map = cam_cc_parent_map_1,
1018 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1019 .clkr.hw.init = &(const struct clk_init_data) {
1020 .name = "cam_cc_mclk0_clk_src",
1021 .parent_data = cam_cc_parent_data_1,
1022 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1023 .flags = CLK_SET_RATE_PARENT,
1024 .ops = &clk_rcg2_ops,
1028 static struct clk_rcg2 cam_cc_mclk1_clk_src = {
1029 .cmd_rcgr = 0x1501c,
1032 .parent_map = cam_cc_parent_map_1,
1033 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1034 .clkr.hw.init = &(const struct clk_init_data) {
1035 .name = "cam_cc_mclk1_clk_src",
1036 .parent_data = cam_cc_parent_data_1,
1037 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1038 .flags = CLK_SET_RATE_PARENT,
1039 .ops = &clk_rcg2_ops,
1043 static struct clk_rcg2 cam_cc_mclk2_clk_src = {
1044 .cmd_rcgr = 0x15038,
1047 .parent_map = cam_cc_parent_map_1,
1048 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1049 .clkr.hw.init = &(const struct clk_init_data) {
1050 .name = "cam_cc_mclk2_clk_src",
1051 .parent_data = cam_cc_parent_data_1,
1052 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1053 .flags = CLK_SET_RATE_PARENT,
1054 .ops = &clk_rcg2_ops,
1058 static struct clk_rcg2 cam_cc_mclk3_clk_src = {
1059 .cmd_rcgr = 0x15054,
1062 .parent_map = cam_cc_parent_map_1,
1063 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1064 .clkr.hw.init = &(const struct clk_init_data) {
1065 .name = "cam_cc_mclk3_clk_src",
1066 .parent_data = cam_cc_parent_data_1,
1067 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1068 .flags = CLK_SET_RATE_PARENT,
1069 .ops = &clk_rcg2_ops,
1073 static struct clk_rcg2 cam_cc_mclk4_clk_src = {
1074 .cmd_rcgr = 0x15070,
1077 .parent_map = cam_cc_parent_map_1,
1078 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1079 .clkr.hw.init = &(const struct clk_init_data) {
1080 .name = "cam_cc_mclk4_clk_src",
1081 .parent_data = cam_cc_parent_data_1,
1082 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1083 .flags = CLK_SET_RATE_PARENT,
1084 .ops = &clk_rcg2_ops,
1088 static struct clk_rcg2 cam_cc_mclk5_clk_src = {
1089 .cmd_rcgr = 0x1508c,
1092 .parent_map = cam_cc_parent_map_1,
1093 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1094 .clkr.hw.init = &(const struct clk_init_data) {
1095 .name = "cam_cc_mclk5_clk_src",
1096 .parent_data = cam_cc_parent_data_1,
1097 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1098 .flags = CLK_SET_RATE_PARENT,
1099 .ops = &clk_rcg2_ops,
1103 static struct clk_rcg2 cam_cc_mclk6_clk_src = {
1104 .cmd_rcgr = 0x150a8,
1107 .parent_map = cam_cc_parent_map_1,
1108 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1109 .clkr.hw.init = &(const struct clk_init_data) {
1110 .name = "cam_cc_mclk6_clk_src",
1111 .parent_data = cam_cc_parent_data_1,
1112 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1113 .flags = CLK_SET_RATE_PARENT,
1114 .ops = &clk_rcg2_ops,
1118 static struct clk_rcg2 cam_cc_mclk7_clk_src = {
1119 .cmd_rcgr = 0x150c4,
1122 .parent_map = cam_cc_parent_map_1,
1123 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1124 .clkr.hw.init = &(const struct clk_init_data) {
1125 .name = "cam_cc_mclk7_clk_src",
1126 .parent_data = cam_cc_parent_data_1,
1127 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1128 .flags = CLK_SET_RATE_PARENT,
1129 .ops = &clk_rcg2_ops,
1133 static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = {
1134 F(19200000, P_BI_TCXO, 1, 0, 0),
1135 F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
1136 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
1137 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
1141 static struct clk_rcg2 cam_cc_qdss_debug_clk_src = {
1142 .cmd_rcgr = 0x131bc,
1145 .parent_map = cam_cc_parent_map_0,
1146 .freq_tbl = ftbl_cam_cc_qdss_debug_clk_src,
1147 .clkr.hw.init = &(const struct clk_init_data) {
1148 .name = "cam_cc_qdss_debug_clk_src",
1149 .parent_data = cam_cc_parent_data_0,
1150 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1151 .flags = CLK_SET_RATE_PARENT,
1152 .ops = &clk_rcg2_ops,
1156 static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = {
1157 F(432000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1158 F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1159 F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1160 F(727000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1164 static struct clk_rcg2 cam_cc_sfe_0_clk_src = {
1165 .cmd_rcgr = 0x13064,
1168 .parent_map = cam_cc_parent_map_6,
1169 .freq_tbl = ftbl_cam_cc_sfe_0_clk_src,
1170 .clkr.hw.init = &(const struct clk_init_data) {
1171 .name = "cam_cc_sfe_0_clk_src",
1172 .parent_data = cam_cc_parent_data_6,
1173 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
1174 .flags = CLK_SET_RATE_PARENT,
1175 .ops = &clk_rcg2_ops,
1179 static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = {
1180 F(432000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1181 F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1182 F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1183 F(727000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1187 static struct clk_rcg2 cam_cc_sfe_1_clk_src = {
1188 .cmd_rcgr = 0x130ac,
1191 .parent_map = cam_cc_parent_map_7,
1192 .freq_tbl = ftbl_cam_cc_sfe_1_clk_src,
1193 .clkr.hw.init = &(const struct clk_init_data) {
1194 .name = "cam_cc_sfe_1_clk_src",
1195 .parent_data = cam_cc_parent_data_7,
1196 .num_parents = ARRAY_SIZE(cam_cc_parent_data_7),
1197 .flags = CLK_SET_RATE_PARENT,
1198 .ops = &clk_rcg2_ops,
1202 static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
1203 F(32000, P_SLEEP_CLK, 1, 0, 0),
1207 static struct clk_rcg2 cam_cc_sleep_clk_src = {
1208 .cmd_rcgr = 0x13210,
1211 .parent_map = cam_cc_parent_map_8,
1212 .freq_tbl = ftbl_cam_cc_sleep_clk_src,
1213 .clkr.hw.init = &(const struct clk_init_data) {
1214 .name = "cam_cc_sleep_clk_src",
1215 .parent_data = cam_cc_parent_data_8,
1216 .num_parents = ARRAY_SIZE(cam_cc_parent_data_8),
1217 .flags = CLK_SET_RATE_PARENT,
1218 .ops = &clk_rcg2_ops,
1222 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
1223 F(19200000, P_BI_TCXO, 1, 0, 0),
1224 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
1228 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
1229 .cmd_rcgr = 0x10034,
1232 .parent_map = cam_cc_parent_map_0,
1233 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
1234 .clkr.hw.init = &(const struct clk_init_data) {
1235 .name = "cam_cc_slow_ahb_clk_src",
1236 .parent_data = cam_cc_parent_data_0,
1237 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1238 .flags = CLK_SET_RATE_PARENT,
1239 .ops = &clk_rcg2_ops,
1243 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
1244 F(19200000, P_BI_TCXO, 1, 0, 0),
1248 static struct clk_rcg2 cam_cc_xo_clk_src = {
1249 .cmd_rcgr = 0x131f4,
1252 .parent_map = cam_cc_parent_map_9,
1253 .freq_tbl = ftbl_cam_cc_xo_clk_src,
1254 .clkr.hw.init = &(const struct clk_init_data) {
1255 .name = "cam_cc_xo_clk_src",
1256 .parent_data = cam_cc_parent_data_9_ao,
1257 .num_parents = ARRAY_SIZE(cam_cc_parent_data_9_ao),
1258 .flags = CLK_SET_RATE_PARENT,
1259 .ops = &clk_rcg2_ops,
1263 static struct clk_branch cam_cc_gdsc_clk = {
1264 .halt_reg = 0x1320c,
1265 .halt_check = BRANCH_HALT,
1267 .enable_reg = 0x1320c,
1268 .enable_mask = BIT(0),
1269 .hw.init = &(const struct clk_init_data) {
1270 .name = "cam_cc_gdsc_clk",
1271 .parent_hws = (const struct clk_hw*[]) {
1272 &cam_cc_xo_clk_src.clkr.hw,
1275 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1276 .ops = &clk_branch2_ops,
1281 static struct clk_branch cam_cc_bps_ahb_clk = {
1282 .halt_reg = 0x1004c,
1283 .halt_check = BRANCH_HALT,
1285 .enable_reg = 0x1004c,
1286 .enable_mask = BIT(0),
1287 .hw.init = &(const struct clk_init_data) {
1288 .name = "cam_cc_bps_ahb_clk",
1289 .parent_hws = (const struct clk_hw*[]) {
1290 &cam_cc_slow_ahb_clk_src.clkr.hw,
1293 .flags = CLK_SET_RATE_PARENT,
1294 .ops = &clk_branch2_ops,
1299 static struct clk_branch cam_cc_bps_clk = {
1300 .halt_reg = 0x10068,
1301 .halt_check = BRANCH_HALT,
1303 .enable_reg = 0x10068,
1304 .enable_mask = BIT(0),
1305 .hw.init = &(const struct clk_init_data) {
1306 .name = "cam_cc_bps_clk",
1307 .parent_hws = (const struct clk_hw*[]) {
1308 &cam_cc_bps_clk_src.clkr.hw,
1311 .flags = CLK_SET_RATE_PARENT,
1312 .ops = &clk_branch2_ops,
1317 static struct clk_branch cam_cc_bps_fast_ahb_clk = {
1318 .halt_reg = 0x10030,
1319 .halt_check = BRANCH_HALT,
1321 .enable_reg = 0x10030,
1322 .enable_mask = BIT(0),
1323 .hw.init = &(const struct clk_init_data) {
1324 .name = "cam_cc_bps_fast_ahb_clk",
1325 .parent_hws = (const struct clk_hw*[]) {
1326 &cam_cc_fast_ahb_clk_src.clkr.hw,
1329 .flags = CLK_SET_RATE_PARENT,
1330 .ops = &clk_branch2_ops,
1335 static struct clk_branch cam_cc_camnoc_axi_clk = {
1336 .halt_reg = 0x131ac,
1337 .halt_check = BRANCH_HALT,
1339 .enable_reg = 0x131ac,
1340 .enable_mask = BIT(0),
1341 .hw.init = &(const struct clk_init_data) {
1342 .name = "cam_cc_camnoc_axi_clk",
1343 .parent_hws = (const struct clk_hw*[]) {
1344 &cam_cc_camnoc_axi_clk_src.clkr.hw,
1347 .flags = CLK_SET_RATE_PARENT,
1348 .ops = &clk_branch2_ops,
1353 static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
1354 .halt_reg = 0x131b4,
1355 .halt_check = BRANCH_HALT,
1357 .enable_reg = 0x131b4,
1358 .enable_mask = BIT(0),
1359 .hw.init = &(const struct clk_init_data) {
1360 .name = "cam_cc_camnoc_dcd_xo_clk",
1361 .parent_hws = (const struct clk_hw*[]) {
1362 &cam_cc_xo_clk_src.clkr.hw,
1365 .flags = CLK_SET_RATE_PARENT,
1366 .ops = &clk_branch2_ops,
1371 static struct clk_branch cam_cc_cci_0_clk = {
1372 .halt_reg = 0x13144,
1373 .halt_check = BRANCH_HALT,
1375 .enable_reg = 0x13144,
1376 .enable_mask = BIT(0),
1377 .hw.init = &(const struct clk_init_data) {
1378 .name = "cam_cc_cci_0_clk",
1379 .parent_hws = (const struct clk_hw*[]) {
1380 &cam_cc_cci_0_clk_src.clkr.hw,
1383 .flags = CLK_SET_RATE_PARENT,
1384 .ops = &clk_branch2_ops,
1389 static struct clk_branch cam_cc_cci_1_clk = {
1390 .halt_reg = 0x13160,
1391 .halt_check = BRANCH_HALT,
1393 .enable_reg = 0x13160,
1394 .enable_mask = BIT(0),
1395 .hw.init = &(const struct clk_init_data) {
1396 .name = "cam_cc_cci_1_clk",
1397 .parent_hws = (const struct clk_hw*[]) {
1398 &cam_cc_cci_1_clk_src.clkr.hw,
1401 .flags = CLK_SET_RATE_PARENT,
1402 .ops = &clk_branch2_ops,
1407 static struct clk_branch cam_cc_core_ahb_clk = {
1408 .halt_reg = 0x131f0,
1409 .halt_check = BRANCH_HALT_DELAY,
1411 .enable_reg = 0x131f0,
1412 .enable_mask = BIT(0),
1413 .hw.init = &(const struct clk_init_data) {
1414 .name = "cam_cc_core_ahb_clk",
1415 .parent_hws = (const struct clk_hw*[]) {
1416 &cam_cc_slow_ahb_clk_src.clkr.hw,
1419 .flags = CLK_SET_RATE_PARENT,
1420 .ops = &clk_branch2_ops,
1425 static struct clk_branch cam_cc_cpas_ahb_clk = {
1426 .halt_reg = 0x13164,
1427 .halt_check = BRANCH_HALT,
1429 .enable_reg = 0x13164,
1430 .enable_mask = BIT(0),
1431 .hw.init = &(const struct clk_init_data) {
1432 .name = "cam_cc_cpas_ahb_clk",
1433 .parent_hws = (const struct clk_hw*[]) {
1434 &cam_cc_slow_ahb_clk_src.clkr.hw,
1437 .flags = CLK_SET_RATE_PARENT,
1438 .ops = &clk_branch2_ops,
1443 static struct clk_branch cam_cc_cpas_bps_clk = {
1444 .halt_reg = 0x10070,
1445 .halt_check = BRANCH_HALT,
1447 .enable_reg = 0x10070,
1448 .enable_mask = BIT(0),
1449 .hw.init = &(const struct clk_init_data) {
1450 .name = "cam_cc_cpas_bps_clk",
1451 .parent_hws = (const struct clk_hw*[]) {
1452 &cam_cc_bps_clk_src.clkr.hw,
1455 .flags = CLK_SET_RATE_PARENT,
1456 .ops = &clk_branch2_ops,
1461 static struct clk_branch cam_cc_cpas_fast_ahb_clk = {
1462 .halt_reg = 0x1316c,
1463 .halt_check = BRANCH_HALT,
1465 .enable_reg = 0x1316c,
1466 .enable_mask = BIT(0),
1467 .hw.init = &(const struct clk_init_data) {
1468 .name = "cam_cc_cpas_fast_ahb_clk",
1469 .parent_hws = (const struct clk_hw*[]) {
1470 &cam_cc_fast_ahb_clk_src.clkr.hw,
1473 .flags = CLK_SET_RATE_PARENT,
1474 .ops = &clk_branch2_ops,
1479 static struct clk_branch cam_cc_cpas_ife_0_clk = {
1480 .halt_reg = 0x11038,
1481 .halt_check = BRANCH_HALT,
1483 .enable_reg = 0x11038,
1484 .enable_mask = BIT(0),
1485 .hw.init = &(const struct clk_init_data) {
1486 .name = "cam_cc_cpas_ife_0_clk",
1487 .parent_hws = (const struct clk_hw*[]) {
1488 &cam_cc_ife_0_clk_src.clkr.hw,
1491 .flags = CLK_SET_RATE_PARENT,
1492 .ops = &clk_branch2_ops,
1497 static struct clk_branch cam_cc_cpas_ife_1_clk = {
1498 .halt_reg = 0x12038,
1499 .halt_check = BRANCH_HALT,
1501 .enable_reg = 0x12038,
1502 .enable_mask = BIT(0),
1503 .hw.init = &(const struct clk_init_data) {
1504 .name = "cam_cc_cpas_ife_1_clk",
1505 .parent_hws = (const struct clk_hw*[]) {
1506 &cam_cc_ife_1_clk_src.clkr.hw,
1509 .flags = CLK_SET_RATE_PARENT,
1510 .ops = &clk_branch2_ops,
1515 static struct clk_branch cam_cc_cpas_ife_2_clk = {
1516 .halt_reg = 0x12084,
1517 .halt_check = BRANCH_HALT,
1519 .enable_reg = 0x12084,
1520 .enable_mask = BIT(0),
1521 .hw.init = &(const struct clk_init_data) {
1522 .name = "cam_cc_cpas_ife_2_clk",
1523 .parent_hws = (const struct clk_hw*[]) {
1524 &cam_cc_ife_2_clk_src.clkr.hw,
1527 .flags = CLK_SET_RATE_PARENT,
1528 .ops = &clk_branch2_ops,
1533 static struct clk_branch cam_cc_cpas_ife_lite_clk = {
1534 .halt_reg = 0x13020,
1535 .halt_check = BRANCH_HALT,
1537 .enable_reg = 0x13020,
1538 .enable_mask = BIT(0),
1539 .hw.init = &(const struct clk_init_data) {
1540 .name = "cam_cc_cpas_ife_lite_clk",
1541 .parent_hws = (const struct clk_hw*[]) {
1542 &cam_cc_ife_lite_clk_src.clkr.hw,
1545 .flags = CLK_SET_RATE_PARENT,
1546 .ops = &clk_branch2_ops,
1551 static struct clk_branch cam_cc_cpas_ipe_nps_clk = {
1552 .halt_reg = 0x100ac,
1553 .halt_check = BRANCH_HALT,
1555 .enable_reg = 0x100ac,
1556 .enable_mask = BIT(0),
1557 .hw.init = &(const struct clk_init_data) {
1558 .name = "cam_cc_cpas_ipe_nps_clk",
1559 .parent_hws = (const struct clk_hw*[]) {
1560 &cam_cc_ipe_nps_clk_src.clkr.hw,
1563 .flags = CLK_SET_RATE_PARENT,
1564 .ops = &clk_branch2_ops,
1569 static struct clk_branch cam_cc_cpas_sbi_clk = {
1570 .halt_reg = 0x100ec,
1571 .halt_check = BRANCH_HALT,
1573 .enable_reg = 0x100ec,
1574 .enable_mask = BIT(0),
1575 .hw.init = &(const struct clk_init_data) {
1576 .name = "cam_cc_cpas_sbi_clk",
1577 .parent_hws = (const struct clk_hw*[]) {
1578 &cam_cc_ife_0_clk_src.clkr.hw,
1581 .flags = CLK_SET_RATE_PARENT,
1582 .ops = &clk_branch2_ops,
1587 static struct clk_branch cam_cc_cpas_sfe_0_clk = {
1588 .halt_reg = 0x13084,
1589 .halt_check = BRANCH_HALT,
1591 .enable_reg = 0x13084,
1592 .enable_mask = BIT(0),
1593 .hw.init = &(const struct clk_init_data) {
1594 .name = "cam_cc_cpas_sfe_0_clk",
1595 .parent_hws = (const struct clk_hw*[]) {
1596 &cam_cc_sfe_0_clk_src.clkr.hw,
1599 .flags = CLK_SET_RATE_PARENT,
1600 .ops = &clk_branch2_ops,
1605 static struct clk_branch cam_cc_cpas_sfe_1_clk = {
1606 .halt_reg = 0x130cc,
1607 .halt_check = BRANCH_HALT,
1609 .enable_reg = 0x130cc,
1610 .enable_mask = BIT(0),
1611 .hw.init = &(const struct clk_init_data) {
1612 .name = "cam_cc_cpas_sfe_1_clk",
1613 .parent_hws = (const struct clk_hw*[]) {
1614 &cam_cc_sfe_1_clk_src.clkr.hw,
1617 .flags = CLK_SET_RATE_PARENT,
1618 .ops = &clk_branch2_ops,
1623 static struct clk_branch cam_cc_csi0phytimer_clk = {
1624 .halt_reg = 0x150f8,
1625 .halt_check = BRANCH_HALT,
1627 .enable_reg = 0x150f8,
1628 .enable_mask = BIT(0),
1629 .hw.init = &(const struct clk_init_data) {
1630 .name = "cam_cc_csi0phytimer_clk",
1631 .parent_hws = (const struct clk_hw*[]) {
1632 &cam_cc_csi0phytimer_clk_src.clkr.hw,
1635 .flags = CLK_SET_RATE_PARENT,
1636 .ops = &clk_branch2_ops,
1641 static struct clk_branch cam_cc_csi1phytimer_clk = {
1642 .halt_reg = 0x1511c,
1643 .halt_check = BRANCH_HALT,
1645 .enable_reg = 0x1511c,
1646 .enable_mask = BIT(0),
1647 .hw.init = &(const struct clk_init_data) {
1648 .name = "cam_cc_csi1phytimer_clk",
1649 .parent_hws = (const struct clk_hw*[]) {
1650 &cam_cc_csi1phytimer_clk_src.clkr.hw,
1653 .flags = CLK_SET_RATE_PARENT,
1654 .ops = &clk_branch2_ops,
1659 static struct clk_branch cam_cc_csi2phytimer_clk = {
1660 .halt_reg = 0x1513c,
1661 .halt_check = BRANCH_HALT,
1663 .enable_reg = 0x1513c,
1664 .enable_mask = BIT(0),
1665 .hw.init = &(const struct clk_init_data) {
1666 .name = "cam_cc_csi2phytimer_clk",
1667 .parent_hws = (const struct clk_hw*[]) {
1668 &cam_cc_csi2phytimer_clk_src.clkr.hw,
1671 .flags = CLK_SET_RATE_PARENT,
1672 .ops = &clk_branch2_ops,
1677 static struct clk_branch cam_cc_csi3phytimer_clk = {
1678 .halt_reg = 0x15164,
1679 .halt_check = BRANCH_HALT,
1681 .enable_reg = 0x15164,
1682 .enable_mask = BIT(0),
1683 .hw.init = &(const struct clk_init_data) {
1684 .name = "cam_cc_csi3phytimer_clk",
1685 .parent_hws = (const struct clk_hw*[]) {
1686 &cam_cc_csi3phytimer_clk_src.clkr.hw,
1689 .flags = CLK_SET_RATE_PARENT,
1690 .ops = &clk_branch2_ops,
1695 static struct clk_branch cam_cc_csi4phytimer_clk = {
1696 .halt_reg = 0x15184,
1697 .halt_check = BRANCH_HALT,
1699 .enable_reg = 0x15184,
1700 .enable_mask = BIT(0),
1701 .hw.init = &(const struct clk_init_data) {
1702 .name = "cam_cc_csi4phytimer_clk",
1703 .parent_hws = (const struct clk_hw*[]) {
1704 &cam_cc_csi4phytimer_clk_src.clkr.hw,
1707 .flags = CLK_SET_RATE_PARENT,
1708 .ops = &clk_branch2_ops,
1713 static struct clk_branch cam_cc_csi5phytimer_clk = {
1714 .halt_reg = 0x151a4,
1715 .halt_check = BRANCH_HALT,
1717 .enable_reg = 0x151a4,
1718 .enable_mask = BIT(0),
1719 .hw.init = &(const struct clk_init_data) {
1720 .name = "cam_cc_csi5phytimer_clk",
1721 .parent_hws = (const struct clk_hw*[]) {
1722 &cam_cc_csi5phytimer_clk_src.clkr.hw,
1725 .flags = CLK_SET_RATE_PARENT,
1726 .ops = &clk_branch2_ops,
1731 static struct clk_branch cam_cc_csid_clk = {
1732 .halt_reg = 0x1318c,
1733 .halt_check = BRANCH_HALT,
1735 .enable_reg = 0x1318c,
1736 .enable_mask = BIT(0),
1737 .hw.init = &(const struct clk_init_data) {
1738 .name = "cam_cc_csid_clk",
1739 .parent_hws = (const struct clk_hw*[]) {
1740 &cam_cc_csid_clk_src.clkr.hw,
1743 .flags = CLK_SET_RATE_PARENT,
1744 .ops = &clk_branch2_ops,
1749 static struct clk_branch cam_cc_csid_csiphy_rx_clk = {
1750 .halt_reg = 0x15100,
1751 .halt_check = BRANCH_HALT,
1753 .enable_reg = 0x15100,
1754 .enable_mask = BIT(0),
1755 .hw.init = &(const struct clk_init_data) {
1756 .name = "cam_cc_csid_csiphy_rx_clk",
1757 .parent_hws = (const struct clk_hw*[]) {
1758 &cam_cc_cphy_rx_clk_src.clkr.hw,
1761 .flags = CLK_SET_RATE_PARENT,
1762 .ops = &clk_branch2_ops,
1767 static struct clk_branch cam_cc_csiphy0_clk = {
1768 .halt_reg = 0x150fc,
1769 .halt_check = BRANCH_HALT,
1771 .enable_reg = 0x150fc,
1772 .enable_mask = BIT(0),
1773 .hw.init = &(const struct clk_init_data) {
1774 .name = "cam_cc_csiphy0_clk",
1775 .parent_hws = (const struct clk_hw*[]) {
1776 &cam_cc_cphy_rx_clk_src.clkr.hw,
1779 .flags = CLK_SET_RATE_PARENT,
1780 .ops = &clk_branch2_ops,
1785 static struct clk_branch cam_cc_csiphy1_clk = {
1786 .halt_reg = 0x15120,
1787 .halt_check = BRANCH_HALT,
1789 .enable_reg = 0x15120,
1790 .enable_mask = BIT(0),
1791 .hw.init = &(const struct clk_init_data) {
1792 .name = "cam_cc_csiphy1_clk",
1793 .parent_hws = (const struct clk_hw*[]) {
1794 &cam_cc_cphy_rx_clk_src.clkr.hw,
1797 .flags = CLK_SET_RATE_PARENT,
1798 .ops = &clk_branch2_ops,
1803 static struct clk_branch cam_cc_csiphy2_clk = {
1804 .halt_reg = 0x15140,
1805 .halt_check = BRANCH_HALT,
1807 .enable_reg = 0x15140,
1808 .enable_mask = BIT(0),
1809 .hw.init = &(const struct clk_init_data) {
1810 .name = "cam_cc_csiphy2_clk",
1811 .parent_hws = (const struct clk_hw*[]) {
1812 &cam_cc_cphy_rx_clk_src.clkr.hw,
1815 .flags = CLK_SET_RATE_PARENT,
1816 .ops = &clk_branch2_ops,
1821 static struct clk_branch cam_cc_csiphy3_clk = {
1822 .halt_reg = 0x15168,
1823 .halt_check = BRANCH_HALT,
1825 .enable_reg = 0x15168,
1826 .enable_mask = BIT(0),
1827 .hw.init = &(const struct clk_init_data) {
1828 .name = "cam_cc_csiphy3_clk",
1829 .parent_hws = (const struct clk_hw*[]) {
1830 &cam_cc_cphy_rx_clk_src.clkr.hw,
1833 .flags = CLK_SET_RATE_PARENT,
1834 .ops = &clk_branch2_ops,
1839 static struct clk_branch cam_cc_csiphy4_clk = {
1840 .halt_reg = 0x15188,
1841 .halt_check = BRANCH_HALT,
1843 .enable_reg = 0x15188,
1844 .enable_mask = BIT(0),
1845 .hw.init = &(const struct clk_init_data) {
1846 .name = "cam_cc_csiphy4_clk",
1847 .parent_hws = (const struct clk_hw*[]) {
1848 &cam_cc_cphy_rx_clk_src.clkr.hw,
1851 .flags = CLK_SET_RATE_PARENT,
1852 .ops = &clk_branch2_ops,
1857 static struct clk_branch cam_cc_csiphy5_clk = {
1858 .halt_reg = 0x151a8,
1859 .halt_check = BRANCH_HALT,
1861 .enable_reg = 0x151a8,
1862 .enable_mask = BIT(0),
1863 .hw.init = &(const struct clk_init_data) {
1864 .name = "cam_cc_csiphy5_clk",
1865 .parent_hws = (const struct clk_hw*[]) {
1866 &cam_cc_cphy_rx_clk_src.clkr.hw,
1869 .flags = CLK_SET_RATE_PARENT,
1870 .ops = &clk_branch2_ops,
1875 static struct clk_branch cam_cc_icp_ahb_clk = {
1876 .halt_reg = 0x13128,
1877 .halt_check = BRANCH_HALT,
1879 .enable_reg = 0x13128,
1880 .enable_mask = BIT(0),
1881 .hw.init = &(const struct clk_init_data) {
1882 .name = "cam_cc_icp_ahb_clk",
1883 .parent_hws = (const struct clk_hw*[]) {
1884 &cam_cc_slow_ahb_clk_src.clkr.hw,
1887 .flags = CLK_SET_RATE_PARENT,
1888 .ops = &clk_branch2_ops,
1893 static struct clk_branch cam_cc_icp_clk = {
1894 .halt_reg = 0x13120,
1895 .halt_check = BRANCH_HALT,
1897 .enable_reg = 0x13120,
1898 .enable_mask = BIT(0),
1899 .hw.init = &(const struct clk_init_data) {
1900 .name = "cam_cc_icp_clk",
1901 .parent_hws = (const struct clk_hw*[]) {
1902 &cam_cc_icp_clk_src.clkr.hw,
1905 .flags = CLK_SET_RATE_PARENT,
1906 .ops = &clk_branch2_ops,
1911 static struct clk_branch cam_cc_ife_0_clk = {
1912 .halt_reg = 0x11030,
1913 .halt_check = BRANCH_HALT,
1915 .enable_reg = 0x11030,
1916 .enable_mask = BIT(0),
1917 .hw.init = &(const struct clk_init_data) {
1918 .name = "cam_cc_ife_0_clk",
1919 .parent_hws = (const struct clk_hw*[]) {
1920 &cam_cc_ife_0_clk_src.clkr.hw,
1923 .flags = CLK_SET_RATE_PARENT,
1924 .ops = &clk_branch2_ops,
1929 static struct clk_branch cam_cc_ife_0_dsp_clk = {
1930 .halt_reg = 0x1103c,
1931 .halt_check = BRANCH_HALT,
1933 .enable_reg = 0x1103c,
1934 .enable_mask = BIT(0),
1935 .hw.init = &(const struct clk_init_data) {
1936 .name = "cam_cc_ife_0_dsp_clk",
1937 .parent_hws = (const struct clk_hw*[]) {
1938 &cam_cc_ife_0_clk_src.clkr.hw,
1941 .flags = CLK_SET_RATE_PARENT,
1942 .ops = &clk_branch2_ops,
1947 static struct clk_branch cam_cc_ife_0_fast_ahb_clk = {
1948 .halt_reg = 0x11048,
1949 .halt_check = BRANCH_HALT,
1951 .enable_reg = 0x11048,
1952 .enable_mask = BIT(0),
1953 .hw.init = &(const struct clk_init_data) {
1954 .name = "cam_cc_ife_0_fast_ahb_clk",
1955 .parent_hws = (const struct clk_hw*[]) {
1956 &cam_cc_fast_ahb_clk_src.clkr.hw,
1959 .flags = CLK_SET_RATE_PARENT,
1960 .ops = &clk_branch2_ops,
1965 static struct clk_branch cam_cc_ife_1_clk = {
1966 .halt_reg = 0x12030,
1967 .halt_check = BRANCH_HALT,
1969 .enable_reg = 0x12030,
1970 .enable_mask = BIT(0),
1971 .hw.init = &(const struct clk_init_data) {
1972 .name = "cam_cc_ife_1_clk",
1973 .parent_hws = (const struct clk_hw*[]) {
1974 &cam_cc_ife_1_clk_src.clkr.hw,
1977 .flags = CLK_SET_RATE_PARENT,
1978 .ops = &clk_branch2_ops,
1983 static struct clk_branch cam_cc_ife_1_dsp_clk = {
1984 .halt_reg = 0x1203c,
1985 .halt_check = BRANCH_HALT,
1987 .enable_reg = 0x1203c,
1988 .enable_mask = BIT(0),
1989 .hw.init = &(const struct clk_init_data) {
1990 .name = "cam_cc_ife_1_dsp_clk",
1991 .parent_hws = (const struct clk_hw*[]) {
1992 &cam_cc_ife_1_clk_src.clkr.hw,
1995 .flags = CLK_SET_RATE_PARENT,
1996 .ops = &clk_branch2_ops,
2001 static struct clk_branch cam_cc_ife_1_fast_ahb_clk = {
2002 .halt_reg = 0x12048,
2003 .halt_check = BRANCH_HALT,
2005 .enable_reg = 0x12048,
2006 .enable_mask = BIT(0),
2007 .hw.init = &(const struct clk_init_data) {
2008 .name = "cam_cc_ife_1_fast_ahb_clk",
2009 .parent_hws = (const struct clk_hw*[]) {
2010 &cam_cc_fast_ahb_clk_src.clkr.hw,
2013 .flags = CLK_SET_RATE_PARENT,
2014 .ops = &clk_branch2_ops,
2019 static struct clk_branch cam_cc_ife_2_clk = {
2020 .halt_reg = 0x1207c,
2021 .halt_check = BRANCH_HALT,
2023 .enable_reg = 0x1207c,
2024 .enable_mask = BIT(0),
2025 .hw.init = &(const struct clk_init_data) {
2026 .name = "cam_cc_ife_2_clk",
2027 .parent_hws = (const struct clk_hw*[]) {
2028 &cam_cc_ife_2_clk_src.clkr.hw,
2031 .flags = CLK_SET_RATE_PARENT,
2032 .ops = &clk_branch2_ops,
2037 static struct clk_branch cam_cc_ife_2_dsp_clk = {
2038 .halt_reg = 0x12088,
2039 .halt_check = BRANCH_HALT,
2041 .enable_reg = 0x12088,
2042 .enable_mask = BIT(0),
2043 .hw.init = &(const struct clk_init_data) {
2044 .name = "cam_cc_ife_2_dsp_clk",
2045 .parent_hws = (const struct clk_hw*[]) {
2046 &cam_cc_ife_2_clk_src.clkr.hw,
2049 .flags = CLK_SET_RATE_PARENT,
2050 .ops = &clk_branch2_ops,
2055 static struct clk_branch cam_cc_ife_2_fast_ahb_clk = {
2056 .halt_reg = 0x12094,
2057 .halt_check = BRANCH_HALT,
2059 .enable_reg = 0x12094,
2060 .enable_mask = BIT(0),
2061 .hw.init = &(const struct clk_init_data) {
2062 .name = "cam_cc_ife_2_fast_ahb_clk",
2063 .parent_hws = (const struct clk_hw*[]) {
2064 &cam_cc_fast_ahb_clk_src.clkr.hw,
2067 .flags = CLK_SET_RATE_PARENT,
2068 .ops = &clk_branch2_ops,
2073 static struct clk_branch cam_cc_ife_lite_ahb_clk = {
2074 .halt_reg = 0x13048,
2075 .halt_check = BRANCH_HALT,
2077 .enable_reg = 0x13048,
2078 .enable_mask = BIT(0),
2079 .hw.init = &(const struct clk_init_data) {
2080 .name = "cam_cc_ife_lite_ahb_clk",
2081 .parent_hws = (const struct clk_hw*[]) {
2082 &cam_cc_slow_ahb_clk_src.clkr.hw,
2085 .flags = CLK_SET_RATE_PARENT,
2086 .ops = &clk_branch2_ops,
2091 static struct clk_branch cam_cc_ife_lite_clk = {
2092 .halt_reg = 0x13018,
2093 .halt_check = BRANCH_HALT,
2095 .enable_reg = 0x13018,
2096 .enable_mask = BIT(0),
2097 .hw.init = &(const struct clk_init_data) {
2098 .name = "cam_cc_ife_lite_clk",
2099 .parent_hws = (const struct clk_hw*[]) {
2100 &cam_cc_ife_lite_clk_src.clkr.hw,
2103 .flags = CLK_SET_RATE_PARENT,
2104 .ops = &clk_branch2_ops,
2109 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
2110 .halt_reg = 0x13044,
2111 .halt_check = BRANCH_HALT,
2113 .enable_reg = 0x13044,
2114 .enable_mask = BIT(0),
2115 .hw.init = &(const struct clk_init_data) {
2116 .name = "cam_cc_ife_lite_cphy_rx_clk",
2117 .parent_hws = (const struct clk_hw*[]) {
2118 &cam_cc_cphy_rx_clk_src.clkr.hw,
2121 .flags = CLK_SET_RATE_PARENT,
2122 .ops = &clk_branch2_ops,
2127 static struct clk_branch cam_cc_ife_lite_csid_clk = {
2128 .halt_reg = 0x1303c,
2129 .halt_check = BRANCH_HALT,
2131 .enable_reg = 0x1303c,
2132 .enable_mask = BIT(0),
2133 .hw.init = &(const struct clk_init_data) {
2134 .name = "cam_cc_ife_lite_csid_clk",
2135 .parent_hws = (const struct clk_hw*[]) {
2136 &cam_cc_ife_lite_csid_clk_src.clkr.hw,
2139 .flags = CLK_SET_RATE_PARENT,
2140 .ops = &clk_branch2_ops,
2145 static struct clk_branch cam_cc_ipe_nps_ahb_clk = {
2146 .halt_reg = 0x100c0,
2147 .halt_check = BRANCH_HALT,
2149 .enable_reg = 0x100c0,
2150 .enable_mask = BIT(0),
2151 .hw.init = &(const struct clk_init_data) {
2152 .name = "cam_cc_ipe_nps_ahb_clk",
2153 .parent_hws = (const struct clk_hw*[]) {
2154 &cam_cc_slow_ahb_clk_src.clkr.hw,
2157 .flags = CLK_SET_RATE_PARENT,
2158 .ops = &clk_branch2_ops,
2163 static struct clk_branch cam_cc_ipe_nps_clk = {
2164 .halt_reg = 0x100a4,
2165 .halt_check = BRANCH_HALT,
2167 .enable_reg = 0x100a4,
2168 .enable_mask = BIT(0),
2169 .hw.init = &(const struct clk_init_data) {
2170 .name = "cam_cc_ipe_nps_clk",
2171 .parent_hws = (const struct clk_hw*[]) {
2172 &cam_cc_ipe_nps_clk_src.clkr.hw,
2175 .flags = CLK_SET_RATE_PARENT,
2176 .ops = &clk_branch2_ops,
2181 static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = {
2182 .halt_reg = 0x100c4,
2183 .halt_check = BRANCH_HALT,
2185 .enable_reg = 0x100c4,
2186 .enable_mask = BIT(0),
2187 .hw.init = &(const struct clk_init_data) {
2188 .name = "cam_cc_ipe_nps_fast_ahb_clk",
2189 .parent_hws = (const struct clk_hw*[]) {
2190 &cam_cc_fast_ahb_clk_src.clkr.hw,
2193 .flags = CLK_SET_RATE_PARENT,
2194 .ops = &clk_branch2_ops,
2199 static struct clk_branch cam_cc_ipe_pps_clk = {
2200 .halt_reg = 0x100b0,
2201 .halt_check = BRANCH_HALT,
2203 .enable_reg = 0x100b0,
2204 .enable_mask = BIT(0),
2205 .hw.init = &(const struct clk_init_data) {
2206 .name = "cam_cc_ipe_pps_clk",
2207 .parent_hws = (const struct clk_hw*[]) {
2208 &cam_cc_ipe_nps_clk_src.clkr.hw,
2211 .flags = CLK_SET_RATE_PARENT,
2212 .ops = &clk_branch2_ops,
2217 static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = {
2218 .halt_reg = 0x100c8,
2219 .halt_check = BRANCH_HALT,
2221 .enable_reg = 0x100c8,
2222 .enable_mask = BIT(0),
2223 .hw.init = &(const struct clk_init_data) {
2224 .name = "cam_cc_ipe_pps_fast_ahb_clk",
2225 .parent_hws = (const struct clk_hw*[]) {
2226 &cam_cc_fast_ahb_clk_src.clkr.hw,
2229 .flags = CLK_SET_RATE_PARENT,
2230 .ops = &clk_branch2_ops,
2235 static struct clk_branch cam_cc_jpeg_clk = {
2236 .halt_reg = 0x130f4,
2237 .halt_check = BRANCH_HALT,
2239 .enable_reg = 0x130f4,
2240 .enable_mask = BIT(0),
2241 .hw.init = &(const struct clk_init_data) {
2242 .name = "cam_cc_jpeg_clk",
2243 .parent_hws = (const struct clk_hw*[]) {
2244 &cam_cc_jpeg_clk_src.clkr.hw,
2247 .flags = CLK_SET_RATE_PARENT,
2248 .ops = &clk_branch2_ops,
2253 static struct clk_branch cam_cc_mclk0_clk = {
2254 .halt_reg = 0x15018,
2255 .halt_check = BRANCH_HALT,
2257 .enable_reg = 0x15018,
2258 .enable_mask = BIT(0),
2259 .hw.init = &(const struct clk_init_data) {
2260 .name = "cam_cc_mclk0_clk",
2261 .parent_hws = (const struct clk_hw*[]) {
2262 &cam_cc_mclk0_clk_src.clkr.hw,
2265 .flags = CLK_SET_RATE_PARENT,
2266 .ops = &clk_branch2_ops,
2271 static struct clk_branch cam_cc_mclk1_clk = {
2272 .halt_reg = 0x15034,
2273 .halt_check = BRANCH_HALT,
2275 .enable_reg = 0x15034,
2276 .enable_mask = BIT(0),
2277 .hw.init = &(const struct clk_init_data) {
2278 .name = "cam_cc_mclk1_clk",
2279 .parent_hws = (const struct clk_hw*[]) {
2280 &cam_cc_mclk1_clk_src.clkr.hw,
2283 .flags = CLK_SET_RATE_PARENT,
2284 .ops = &clk_branch2_ops,
2289 static struct clk_branch cam_cc_mclk2_clk = {
2290 .halt_reg = 0x15050,
2291 .halt_check = BRANCH_HALT,
2293 .enable_reg = 0x15050,
2294 .enable_mask = BIT(0),
2295 .hw.init = &(const struct clk_init_data) {
2296 .name = "cam_cc_mclk2_clk",
2297 .parent_hws = (const struct clk_hw*[]) {
2298 &cam_cc_mclk2_clk_src.clkr.hw,
2301 .flags = CLK_SET_RATE_PARENT,
2302 .ops = &clk_branch2_ops,
2307 static struct clk_branch cam_cc_mclk3_clk = {
2308 .halt_reg = 0x1506c,
2309 .halt_check = BRANCH_HALT,
2311 .enable_reg = 0x1506c,
2312 .enable_mask = BIT(0),
2313 .hw.init = &(const struct clk_init_data) {
2314 .name = "cam_cc_mclk3_clk",
2315 .parent_hws = (const struct clk_hw*[]) {
2316 &cam_cc_mclk3_clk_src.clkr.hw,
2319 .flags = CLK_SET_RATE_PARENT,
2320 .ops = &clk_branch2_ops,
2325 static struct clk_branch cam_cc_mclk4_clk = {
2326 .halt_reg = 0x15088,
2327 .halt_check = BRANCH_HALT,
2329 .enable_reg = 0x15088,
2330 .enable_mask = BIT(0),
2331 .hw.init = &(const struct clk_init_data) {
2332 .name = "cam_cc_mclk4_clk",
2333 .parent_hws = (const struct clk_hw*[]) {
2334 &cam_cc_mclk4_clk_src.clkr.hw,
2337 .flags = CLK_SET_RATE_PARENT,
2338 .ops = &clk_branch2_ops,
2343 static struct clk_branch cam_cc_mclk5_clk = {
2344 .halt_reg = 0x150a4,
2345 .halt_check = BRANCH_HALT,
2347 .enable_reg = 0x150a4,
2348 .enable_mask = BIT(0),
2349 .hw.init = &(const struct clk_init_data) {
2350 .name = "cam_cc_mclk5_clk",
2351 .parent_hws = (const struct clk_hw*[]) {
2352 &cam_cc_mclk5_clk_src.clkr.hw,
2355 .flags = CLK_SET_RATE_PARENT,
2356 .ops = &clk_branch2_ops,
2361 static struct clk_branch cam_cc_mclk6_clk = {
2362 .halt_reg = 0x150c0,
2363 .halt_check = BRANCH_HALT,
2365 .enable_reg = 0x150c0,
2366 .enable_mask = BIT(0),
2367 .hw.init = &(const struct clk_init_data) {
2368 .name = "cam_cc_mclk6_clk",
2369 .parent_hws = (const struct clk_hw*[]) {
2370 &cam_cc_mclk6_clk_src.clkr.hw,
2373 .flags = CLK_SET_RATE_PARENT,
2374 .ops = &clk_branch2_ops,
2379 static struct clk_branch cam_cc_mclk7_clk = {
2380 .halt_reg = 0x150dc,
2381 .halt_check = BRANCH_HALT,
2383 .enable_reg = 0x150dc,
2384 .enable_mask = BIT(0),
2385 .hw.init = &(const struct clk_init_data) {
2386 .name = "cam_cc_mclk7_clk",
2387 .parent_hws = (const struct clk_hw*[]) {
2388 &cam_cc_mclk7_clk_src.clkr.hw,
2391 .flags = CLK_SET_RATE_PARENT,
2392 .ops = &clk_branch2_ops,
2397 static struct clk_branch cam_cc_qdss_debug_clk = {
2398 .halt_reg = 0x131d4,
2399 .halt_check = BRANCH_HALT,
2401 .enable_reg = 0x131d4,
2402 .enable_mask = BIT(0),
2403 .hw.init = &(const struct clk_init_data) {
2404 .name = "cam_cc_qdss_debug_clk",
2405 .parent_hws = (const struct clk_hw*[]) {
2406 &cam_cc_qdss_debug_clk_src.clkr.hw,
2409 .flags = CLK_SET_RATE_PARENT,
2410 .ops = &clk_branch2_ops,
2415 static struct clk_branch cam_cc_qdss_debug_xo_clk = {
2416 .halt_reg = 0x131d8,
2417 .halt_check = BRANCH_HALT,
2419 .enable_reg = 0x131d8,
2420 .enable_mask = BIT(0),
2421 .hw.init = &(const struct clk_init_data) {
2422 .name = "cam_cc_qdss_debug_xo_clk",
2423 .parent_hws = (const struct clk_hw*[]) {
2424 &cam_cc_xo_clk_src.clkr.hw,
2427 .flags = CLK_SET_RATE_PARENT,
2428 .ops = &clk_branch2_ops,
2433 static struct clk_branch cam_cc_sbi_ahb_clk = {
2434 .halt_reg = 0x100f0,
2435 .halt_check = BRANCH_HALT,
2437 .enable_reg = 0x100f0,
2438 .enable_mask = BIT(0),
2439 .hw.init = &(const struct clk_init_data) {
2440 .name = "cam_cc_sbi_ahb_clk",
2441 .parent_hws = (const struct clk_hw*[]) {
2442 &cam_cc_slow_ahb_clk_src.clkr.hw,
2445 .flags = CLK_SET_RATE_PARENT,
2446 .ops = &clk_branch2_ops,
2451 static struct clk_branch cam_cc_sbi_clk = {
2452 .halt_reg = 0x100e4,
2453 .halt_check = BRANCH_HALT,
2455 .enable_reg = 0x100e4,
2456 .enable_mask = BIT(0),
2457 .hw.init = &(const struct clk_init_data) {
2458 .name = "cam_cc_sbi_clk",
2459 .parent_hws = (const struct clk_hw*[]) {
2460 &cam_cc_ife_0_clk_src.clkr.hw,
2463 .flags = CLK_SET_RATE_PARENT,
2464 .ops = &clk_branch2_ops,
2469 static struct clk_branch cam_cc_sfe_0_clk = {
2470 .halt_reg = 0x1307c,
2471 .halt_check = BRANCH_HALT,
2473 .enable_reg = 0x1307c,
2474 .enable_mask = BIT(0),
2475 .hw.init = &(const struct clk_init_data) {
2476 .name = "cam_cc_sfe_0_clk",
2477 .parent_hws = (const struct clk_hw*[]) {
2478 &cam_cc_sfe_0_clk_src.clkr.hw,
2481 .flags = CLK_SET_RATE_PARENT,
2482 .ops = &clk_branch2_ops,
2487 static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = {
2488 .halt_reg = 0x13090,
2489 .halt_check = BRANCH_HALT,
2491 .enable_reg = 0x13090,
2492 .enable_mask = BIT(0),
2493 .hw.init = &(const struct clk_init_data) {
2494 .name = "cam_cc_sfe_0_fast_ahb_clk",
2495 .parent_hws = (const struct clk_hw*[]) {
2496 &cam_cc_fast_ahb_clk_src.clkr.hw,
2499 .flags = CLK_SET_RATE_PARENT,
2500 .ops = &clk_branch2_ops,
2505 static struct clk_branch cam_cc_sfe_1_clk = {
2506 .halt_reg = 0x130c4,
2507 .halt_check = BRANCH_HALT,
2509 .enable_reg = 0x130c4,
2510 .enable_mask = BIT(0),
2511 .hw.init = &(const struct clk_init_data) {
2512 .name = "cam_cc_sfe_1_clk",
2513 .parent_hws = (const struct clk_hw*[]) {
2514 &cam_cc_sfe_1_clk_src.clkr.hw,
2517 .flags = CLK_SET_RATE_PARENT,
2518 .ops = &clk_branch2_ops,
2523 static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
2524 .halt_reg = 0x130d8,
2525 .halt_check = BRANCH_HALT,
2527 .enable_reg = 0x130d8,
2528 .enable_mask = BIT(0),
2529 .hw.init = &(const struct clk_init_data) {
2530 .name = "cam_cc_sfe_1_fast_ahb_clk",
2531 .parent_hws = (const struct clk_hw*[]) {
2532 &cam_cc_fast_ahb_clk_src.clkr.hw,
2535 .flags = CLK_SET_RATE_PARENT,
2536 .ops = &clk_branch2_ops,
2541 static struct clk_branch cam_cc_sleep_clk = {
2542 .halt_reg = 0x13228,
2543 .halt_check = BRANCH_HALT,
2545 .enable_reg = 0x13228,
2546 .enable_mask = BIT(0),
2547 .hw.init = &(const struct clk_init_data) {
2548 .name = "cam_cc_sleep_clk",
2549 .parent_hws = (const struct clk_hw*[]) {
2550 &cam_cc_sleep_clk_src.clkr.hw,
2553 .flags = CLK_SET_RATE_PARENT,
2554 .ops = &clk_branch2_ops,
2559 static struct clk_regmap *cam_cc_sm8450_clocks[] = {
2560 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
2561 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
2562 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
2563 [CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr,
2564 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
2565 [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
2566 [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
2567 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
2568 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
2569 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
2570 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
2571 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
2572 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
2573 [CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr,
2574 [CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr,
2575 [CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr,
2576 [CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr,
2577 [CAM_CC_CPAS_IFE_2_CLK] = &cam_cc_cpas_ife_2_clk.clkr,
2578 [CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr,
2579 [CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr,
2580 [CAM_CC_CPAS_SBI_CLK] = &cam_cc_cpas_sbi_clk.clkr,
2581 [CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr,
2582 [CAM_CC_CPAS_SFE_1_CLK] = &cam_cc_cpas_sfe_1_clk.clkr,
2583 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
2584 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
2585 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
2586 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
2587 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
2588 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
2589 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
2590 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
2591 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
2592 [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
2593 [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
2594 [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr,
2595 [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr,
2596 [CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr,
2597 [CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr,
2598 [CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr,
2599 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
2600 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
2601 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
2602 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
2603 [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
2604 [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr,
2605 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
2606 [CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr,
2607 [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
2608 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
2609 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
2610 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
2611 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
2612 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
2613 [CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr,
2614 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
2615 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
2616 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
2617 [CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr,
2618 [CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr,
2619 [CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr,
2620 [CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr,
2621 [CAM_CC_IFE_2_FAST_AHB_CLK] = &cam_cc_ife_2_fast_ahb_clk.clkr,
2622 [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr,
2623 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
2624 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
2625 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
2626 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
2627 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
2628 [CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr,
2629 [CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr,
2630 [CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr,
2631 [CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr,
2632 [CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr,
2633 [CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr,
2634 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
2635 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
2636 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
2637 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
2638 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
2639 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
2640 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
2641 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
2642 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
2643 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
2644 [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
2645 [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
2646 [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
2647 [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
2648 [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr,
2649 [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr,
2650 [CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr,
2651 [CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr,
2652 [CAM_CC_PLL0] = &cam_cc_pll0.clkr,
2653 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
2654 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
2655 [CAM_CC_PLL1] = &cam_cc_pll1.clkr,
2656 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
2657 [CAM_CC_PLL2] = &cam_cc_pll2.clkr,
2658 [CAM_CC_PLL3] = &cam_cc_pll3.clkr,
2659 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
2660 [CAM_CC_PLL4] = &cam_cc_pll4.clkr,
2661 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
2662 [CAM_CC_PLL5] = &cam_cc_pll5.clkr,
2663 [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr,
2664 [CAM_CC_PLL6] = &cam_cc_pll6.clkr,
2665 [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr,
2666 [CAM_CC_PLL7] = &cam_cc_pll7.clkr,
2667 [CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr,
2668 [CAM_CC_PLL8] = &cam_cc_pll8.clkr,
2669 [CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr,
2670 [CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr,
2671 [CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr,
2672 [CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
2673 [CAM_CC_SBI_AHB_CLK] = &cam_cc_sbi_ahb_clk.clkr,
2674 [CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr,
2675 [CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr,
2676 [CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr,
2677 [CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr,
2678 [CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr,
2679 [CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr,
2680 [CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr,
2681 [CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr,
2682 [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
2683 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
2684 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
2687 static const struct qcom_reset_map cam_cc_sm8450_resets[] = {
2688 [CAM_CC_BPS_BCR] = { 0x10000 },
2689 [CAM_CC_ICP_BCR] = { 0x13104 },
2690 [CAM_CC_IFE_0_BCR] = { 0x11000 },
2691 [CAM_CC_IFE_1_BCR] = { 0x12000 },
2692 [CAM_CC_IFE_2_BCR] = { 0x1204c },
2693 [CAM_CC_IPE_0_BCR] = { 0x10074 },
2694 [CAM_CC_QDSS_DEBUG_BCR] = { 0x131b8 },
2695 [CAM_CC_SBI_BCR] = { 0x100cc },
2696 [CAM_CC_SFE_0_BCR] = { 0x1304c },
2697 [CAM_CC_SFE_1_BCR] = { 0x13094 },
2700 static const struct regmap_config cam_cc_sm8450_regmap_config = {
2704 .max_register = 0x1601c,
2708 static struct gdsc titan_top_gdsc;
2710 static struct gdsc bps_gdsc = {
2715 .flags = HW_CTRL | POLL_CFG_GDSCR,
2716 .pwrsts = PWRSTS_OFF_ON,
2719 static struct gdsc ipe_0_gdsc = {
2722 .name = "ipe_0_gdsc",
2724 .flags = HW_CTRL | POLL_CFG_GDSCR,
2725 .pwrsts = PWRSTS_OFF_ON,
2728 static struct gdsc sbi_gdsc = {
2733 .flags = POLL_CFG_GDSCR,
2734 .pwrsts = PWRSTS_OFF_ON,
2737 static struct gdsc ife_0_gdsc = {
2740 .name = "ife_0_gdsc",
2742 .flags = POLL_CFG_GDSCR,
2743 .parent = &titan_top_gdsc.pd,
2744 .pwrsts = PWRSTS_OFF_ON,
2747 static struct gdsc ife_1_gdsc = {
2750 .name = "ife_1_gdsc",
2752 .flags = POLL_CFG_GDSCR,
2753 .parent = &titan_top_gdsc.pd,
2754 .pwrsts = PWRSTS_OFF_ON,
2757 static struct gdsc ife_2_gdsc = {
2760 .name = "ife_2_gdsc",
2762 .flags = POLL_CFG_GDSCR,
2763 .parent = &titan_top_gdsc.pd,
2764 .pwrsts = PWRSTS_OFF_ON,
2767 static struct gdsc sfe_0_gdsc = {
2770 .name = "sfe_0_gdsc",
2772 .flags = POLL_CFG_GDSCR,
2773 .parent = &titan_top_gdsc.pd,
2774 .pwrsts = PWRSTS_OFF_ON,
2777 static struct gdsc sfe_1_gdsc = {
2780 .name = "sfe_1_gdsc",
2782 .flags = POLL_CFG_GDSCR,
2783 .parent = &titan_top_gdsc.pd,
2784 .pwrsts = PWRSTS_OFF_ON,
2787 static struct gdsc titan_top_gdsc = {
2790 .name = "titan_top_gdsc",
2792 .flags = POLL_CFG_GDSCR,
2793 .pwrsts = PWRSTS_OFF_ON,
2796 static struct gdsc *cam_cc_sm8450_gdscs[] = {
2797 [BPS_GDSC] = &bps_gdsc,
2798 [IPE_0_GDSC] = &ipe_0_gdsc,
2799 [SBI_GDSC] = &sbi_gdsc,
2800 [IFE_0_GDSC] = &ife_0_gdsc,
2801 [IFE_1_GDSC] = &ife_1_gdsc,
2802 [IFE_2_GDSC] = &ife_2_gdsc,
2803 [SFE_0_GDSC] = &sfe_0_gdsc,
2804 [SFE_1_GDSC] = &sfe_1_gdsc,
2805 [TITAN_TOP_GDSC] = &titan_top_gdsc,
2808 static const struct qcom_cc_desc cam_cc_sm8450_desc = {
2809 .config = &cam_cc_sm8450_regmap_config,
2810 .clks = cam_cc_sm8450_clocks,
2811 .num_clks = ARRAY_SIZE(cam_cc_sm8450_clocks),
2812 .resets = cam_cc_sm8450_resets,
2813 .num_resets = ARRAY_SIZE(cam_cc_sm8450_resets),
2814 .gdscs = cam_cc_sm8450_gdscs,
2815 .num_gdscs = ARRAY_SIZE(cam_cc_sm8450_gdscs),
2818 static const struct of_device_id cam_cc_sm8450_match_table[] = {
2819 { .compatible = "qcom,sm8450-camcc" },
2822 MODULE_DEVICE_TABLE(of, cam_cc_sm8450_match_table);
2824 static int cam_cc_sm8450_probe(struct platform_device *pdev)
2826 struct regmap *regmap;
2828 regmap = qcom_cc_map(pdev, &cam_cc_sm8450_desc);
2830 return PTR_ERR(regmap);
2832 clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
2833 clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
2834 clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
2835 clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
2836 clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
2837 clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
2838 clk_lucid_evo_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
2839 clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config);
2840 clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config);
2842 return qcom_cc_really_probe(pdev, &cam_cc_sm8450_desc, regmap);
2845 static struct platform_driver cam_cc_sm8450_driver = {
2846 .probe = cam_cc_sm8450_probe,
2848 .name = "camcc-sm8450",
2849 .of_match_table = cam_cc_sm8450_match_table,
2853 module_platform_driver(cam_cc_sm8450_driver);
2855 MODULE_DESCRIPTION("QCOM CAMCC SM8450 Driver");
2856 MODULE_LICENSE("GPL");