1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10 #include <linux/reset-controller.h>
12 #include <dt-bindings/clock/qcom,camcc-sm8250.h>
14 #include "clk-alpha-pll.h"
15 #include "clk-branch.h"
17 #include "clk-regmap-divider.h"
24 P_CAM_CC_PLL0_OUT_EVEN,
25 P_CAM_CC_PLL0_OUT_MAIN,
26 P_CAM_CC_PLL0_OUT_ODD,
27 P_CAM_CC_PLL1_OUT_EVEN,
28 P_CAM_CC_PLL2_OUT_EARLY,
29 P_CAM_CC_PLL2_OUT_MAIN,
30 P_CAM_CC_PLL3_OUT_EVEN,
31 P_CAM_CC_PLL4_OUT_EVEN,
35 static struct pll_vco lucid_vco[] = {
36 { 249600000, 2000000000, 0 },
39 static struct pll_vco zonda_vco[] = {
40 { 595200000UL, 3600000000UL, 0 },
43 static const struct alpha_pll_config cam_cc_pll0_config = {
46 .config_ctl_val = 0x20485699,
47 .config_ctl_hi_val = 0x00002261,
48 .config_ctl_hi1_val = 0x329A699c,
49 .user_ctl_val = 0x00003100,
50 .user_ctl_hi_val = 0x00000805,
51 .user_ctl_hi1_val = 0x00000000,
54 static struct clk_alpha_pll cam_cc_pll0 = {
56 .vco_table = lucid_vco,
57 .num_vco = ARRAY_SIZE(lucid_vco),
58 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
60 .hw.init = &(struct clk_init_data){
61 .name = "cam_cc_pll0",
62 .parent_data = &(const struct clk_parent_data){
66 .ops = &clk_alpha_pll_lucid_ops,
71 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
76 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
79 .post_div_table = post_div_table_cam_cc_pll0_out_even,
80 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
82 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
83 .clkr.hw.init = &(struct clk_init_data){
84 .name = "cam_cc_pll0_out_even",
85 .parent_hws = (const struct clk_hw*[]){
89 .flags = CLK_SET_RATE_PARENT,
90 .ops = &clk_alpha_pll_postdiv_lucid_ops,
94 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
99 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
101 .post_div_shift = 12,
102 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
103 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
105 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
106 .clkr.hw.init = &(struct clk_init_data){
107 .name = "cam_cc_pll0_out_odd",
108 .parent_hws = (const struct clk_hw*[]){
109 &cam_cc_pll0.clkr.hw,
112 .flags = CLK_SET_RATE_PARENT,
113 .ops = &clk_alpha_pll_postdiv_lucid_ops,
117 static const struct alpha_pll_config cam_cc_pll1_config = {
120 .config_ctl_val = 0x20485699,
121 .config_ctl_hi_val = 0x00002261,
122 .config_ctl_hi1_val = 0x329A699c,
123 .user_ctl_val = 0x00000100,
124 .user_ctl_hi_val = 0x00000805,
125 .user_ctl_hi1_val = 0x00000000,
128 static struct clk_alpha_pll cam_cc_pll1 = {
130 .vco_table = lucid_vco,
131 .num_vco = ARRAY_SIZE(lucid_vco),
132 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
134 .hw.init = &(struct clk_init_data){
135 .name = "cam_cc_pll1",
136 .parent_data = &(const struct clk_parent_data){
137 .fw_name = "bi_tcxo",
140 .ops = &clk_alpha_pll_lucid_ops,
145 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
150 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
153 .post_div_table = post_div_table_cam_cc_pll1_out_even,
154 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
156 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
157 .clkr.hw.init = &(struct clk_init_data){
158 .name = "cam_cc_pll1_out_even",
159 .parent_hws = (const struct clk_hw*[]){
160 &cam_cc_pll1.clkr.hw,
163 .flags = CLK_SET_RATE_PARENT,
164 .ops = &clk_alpha_pll_postdiv_lucid_ops,
168 static const struct alpha_pll_config cam_cc_pll2_config = {
171 .config_ctl_val = 0x08200920,
172 .config_ctl_hi_val = 0x05002015,
173 .config_ctl_hi1_val = 0x00000000,
174 .user_ctl_val = 0x00000100,
175 .user_ctl_hi_val = 0x00000000,
176 .user_ctl_hi1_val = 0x00000000,
179 static struct clk_alpha_pll cam_cc_pll2 = {
181 .vco_table = zonda_vco,
182 .num_vco = ARRAY_SIZE(zonda_vco),
183 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
185 .hw.init = &(struct clk_init_data){
186 .name = "cam_cc_pll2",
187 .parent_data = &(const struct clk_parent_data){
188 .fw_name = "bi_tcxo",
191 .ops = &clk_alpha_pll_zonda_ops,
196 static const struct clk_div_table post_div_table_cam_cc_pll2_out_main[] = {
201 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_main = {
204 .post_div_table = post_div_table_cam_cc_pll2_out_main,
205 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_main),
207 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
208 .clkr.hw.init = &(struct clk_init_data){
209 .name = "cam_cc_pll2_out_main",
210 .parent_hws = (const struct clk_hw*[]){
211 &cam_cc_pll2.clkr.hw,
214 .flags = CLK_SET_RATE_PARENT,
215 .ops = &clk_alpha_pll_postdiv_zonda_ops,
219 static const struct alpha_pll_config cam_cc_pll3_config = {
222 .config_ctl_val = 0x20485699,
223 .config_ctl_hi_val = 0x00002261,
224 .config_ctl_hi1_val = 0x329A699c,
225 .user_ctl_val = 0x00000100,
226 .user_ctl_hi_val = 0x00000805,
227 .user_ctl_hi1_val = 0x00000000,
230 static struct clk_alpha_pll cam_cc_pll3 = {
232 .vco_table = lucid_vco,
233 .num_vco = ARRAY_SIZE(lucid_vco),
234 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
236 .hw.init = &(struct clk_init_data){
237 .name = "cam_cc_pll3",
238 .parent_data = &(const struct clk_parent_data){
239 .fw_name = "bi_tcxo",
242 .ops = &clk_alpha_pll_lucid_ops,
247 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
252 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
255 .post_div_table = post_div_table_cam_cc_pll3_out_even,
256 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
258 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
259 .clkr.hw.init = &(struct clk_init_data){
260 .name = "cam_cc_pll3_out_even",
261 .parent_hws = (const struct clk_hw*[]){
262 &cam_cc_pll3.clkr.hw,
265 .flags = CLK_SET_RATE_PARENT,
266 .ops = &clk_alpha_pll_postdiv_lucid_ops,
270 static const struct alpha_pll_config cam_cc_pll4_config = {
273 .config_ctl_val = 0x20485699,
274 .config_ctl_hi_val = 0x00002261,
275 .config_ctl_hi1_val = 0x329A699c,
276 .user_ctl_val = 0x00000100,
277 .user_ctl_hi_val = 0x00000805,
278 .user_ctl_hi1_val = 0x00000000,
281 static struct clk_alpha_pll cam_cc_pll4 = {
283 .vco_table = lucid_vco,
284 .num_vco = ARRAY_SIZE(lucid_vco),
285 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
287 .hw.init = &(struct clk_init_data){
288 .name = "cam_cc_pll4",
289 .parent_data = &(const struct clk_parent_data){
290 .fw_name = "bi_tcxo",
293 .ops = &clk_alpha_pll_lucid_ops,
298 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
303 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
306 .post_div_table = post_div_table_cam_cc_pll4_out_even,
307 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
309 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
310 .clkr.hw.init = &(struct clk_init_data){
311 .name = "cam_cc_pll4_out_even",
312 .parent_hws = (const struct clk_hw*[]){
313 &cam_cc_pll4.clkr.hw,
316 .flags = CLK_SET_RATE_PARENT,
317 .ops = &clk_alpha_pll_postdiv_lucid_ops,
321 static const struct parent_map cam_cc_parent_map_0[] = {
323 { P_CAM_CC_PLL0_OUT_MAIN, 1 },
324 { P_CAM_CC_PLL0_OUT_EVEN, 2 },
325 { P_CAM_CC_PLL0_OUT_ODD, 3 },
326 { P_CAM_CC_PLL2_OUT_MAIN, 5 },
329 static const struct clk_parent_data cam_cc_parent_data_0[] = {
330 { .fw_name = "bi_tcxo" },
331 { .hw = &cam_cc_pll0.clkr.hw },
332 { .hw = &cam_cc_pll0_out_even.clkr.hw },
333 { .hw = &cam_cc_pll0_out_odd.clkr.hw },
334 { .hw = &cam_cc_pll2_out_main.clkr.hw },
337 static const struct parent_map cam_cc_parent_map_1[] = {
339 { P_CAM_CC_PLL2_OUT_EARLY, 5 },
342 static const struct clk_parent_data cam_cc_parent_data_1[] = {
343 { .fw_name = "bi_tcxo" },
344 { .hw = &cam_cc_pll2.clkr.hw },
347 static const struct parent_map cam_cc_parent_map_2[] = {
349 { P_CAM_CC_PLL3_OUT_EVEN, 6 },
352 static const struct clk_parent_data cam_cc_parent_data_2[] = {
353 { .fw_name = "bi_tcxo" },
354 { .hw = &cam_cc_pll3_out_even.clkr.hw },
357 static const struct parent_map cam_cc_parent_map_3[] = {
359 { P_CAM_CC_PLL4_OUT_EVEN, 6 },
362 static const struct clk_parent_data cam_cc_parent_data_3[] = {
363 { .fw_name = "bi_tcxo" },
364 { .hw = &cam_cc_pll4_out_even.clkr.hw },
367 static const struct parent_map cam_cc_parent_map_4[] = {
369 { P_CAM_CC_PLL1_OUT_EVEN, 4 },
372 static const struct clk_parent_data cam_cc_parent_data_4[] = {
373 { .fw_name = "bi_tcxo" },
374 { .hw = &cam_cc_pll1_out_even.clkr.hw },
377 static const struct parent_map cam_cc_parent_map_5[] = {
381 static const struct clk_parent_data cam_cc_parent_data_5[] = {
382 { .fw_name = "sleep_clk" },
385 static const struct parent_map cam_cc_parent_map_6[] = {
389 static const struct clk_parent_data cam_cc_parent_data_6[] = {
390 { .fw_name = "bi_tcxo" },
393 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
394 F(19200000, P_BI_TCXO, 1, 0, 0),
395 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
396 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
397 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
398 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
399 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
403 static struct clk_rcg2 cam_cc_bps_clk_src = {
407 .parent_map = cam_cc_parent_map_0,
408 .freq_tbl = ftbl_cam_cc_bps_clk_src,
409 .clkr.hw.init = &(struct clk_init_data){
410 .name = "cam_cc_bps_clk_src",
411 .parent_data = cam_cc_parent_data_0,
412 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
413 .flags = CLK_SET_RATE_PARENT,
414 .ops = &clk_rcg2_ops,
418 static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
419 F(19200000, P_BI_TCXO, 1, 0, 0),
420 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
421 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
425 static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
429 .parent_map = cam_cc_parent_map_0,
430 .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
431 .clkr.hw.init = &(struct clk_init_data){
432 .name = "cam_cc_camnoc_axi_clk_src",
433 .parent_data = cam_cc_parent_data_0,
434 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
435 .flags = CLK_SET_RATE_PARENT,
436 .ops = &clk_rcg2_ops,
440 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
441 F(19200000, P_BI_TCXO, 1, 0, 0),
442 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
446 static struct clk_rcg2 cam_cc_cci_0_clk_src = {
450 .parent_map = cam_cc_parent_map_0,
451 .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
452 .clkr.hw.init = &(struct clk_init_data){
453 .name = "cam_cc_cci_0_clk_src",
454 .parent_data = cam_cc_parent_data_0,
455 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
456 .flags = CLK_SET_RATE_PARENT,
457 .ops = &clk_rcg2_ops,
461 static struct clk_rcg2 cam_cc_cci_1_clk_src = {
465 .parent_map = cam_cc_parent_map_0,
466 .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
467 .clkr.hw.init = &(struct clk_init_data){
468 .name = "cam_cc_cci_1_clk_src",
469 .parent_data = cam_cc_parent_data_0,
470 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
471 .flags = CLK_SET_RATE_PARENT,
472 .ops = &clk_rcg2_ops,
476 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
477 F(19200000, P_BI_TCXO, 1, 0, 0),
478 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
482 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
486 .parent_map = cam_cc_parent_map_0,
487 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
488 .clkr.hw.init = &(struct clk_init_data){
489 .name = "cam_cc_cphy_rx_clk_src",
490 .parent_data = cam_cc_parent_data_0,
491 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
492 .flags = CLK_SET_RATE_PARENT,
493 .ops = &clk_rcg2_ops,
497 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
498 F(19200000, P_BI_TCXO, 1, 0, 0),
499 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
503 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
507 .parent_map = cam_cc_parent_map_0,
508 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
509 .clkr.hw.init = &(struct clk_init_data){
510 .name = "cam_cc_csi0phytimer_clk_src",
511 .parent_data = cam_cc_parent_data_0,
512 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
513 .flags = CLK_SET_RATE_PARENT,
514 .ops = &clk_rcg2_ops,
518 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
522 .parent_map = cam_cc_parent_map_0,
523 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
524 .clkr.hw.init = &(struct clk_init_data){
525 .name = "cam_cc_csi1phytimer_clk_src",
526 .parent_data = cam_cc_parent_data_0,
527 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
528 .flags = CLK_SET_RATE_PARENT,
529 .ops = &clk_rcg2_ops,
533 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
537 .parent_map = cam_cc_parent_map_0,
538 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
539 .clkr.hw.init = &(struct clk_init_data){
540 .name = "cam_cc_csi2phytimer_clk_src",
541 .parent_data = cam_cc_parent_data_0,
542 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
543 .flags = CLK_SET_RATE_PARENT,
544 .ops = &clk_rcg2_ops,
548 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
552 .parent_map = cam_cc_parent_map_0,
553 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
554 .clkr.hw.init = &(struct clk_init_data){
555 .name = "cam_cc_csi3phytimer_clk_src",
556 .parent_data = cam_cc_parent_data_0,
557 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
558 .flags = CLK_SET_RATE_PARENT,
559 .ops = &clk_rcg2_ops,
563 static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
567 .parent_map = cam_cc_parent_map_0,
568 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
569 .clkr.hw.init = &(struct clk_init_data){
570 .name = "cam_cc_csi4phytimer_clk_src",
571 .parent_data = cam_cc_parent_data_0,
572 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
573 .flags = CLK_SET_RATE_PARENT,
574 .ops = &clk_rcg2_ops,
578 static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = {
582 .parent_map = cam_cc_parent_map_0,
583 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
584 .clkr.hw.init = &(struct clk_init_data){
585 .name = "cam_cc_csi5phytimer_clk_src",
586 .parent_data = cam_cc_parent_data_0,
587 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
588 .flags = CLK_SET_RATE_PARENT,
589 .ops = &clk_rcg2_ops,
593 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
594 F(19200000, P_BI_TCXO, 1, 0, 0),
595 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
596 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
597 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
598 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
599 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
603 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
607 .parent_map = cam_cc_parent_map_0,
608 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
609 .clkr.hw.init = &(struct clk_init_data){
610 .name = "cam_cc_fast_ahb_clk_src",
611 .parent_data = cam_cc_parent_data_0,
612 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
613 .flags = CLK_SET_RATE_PARENT,
614 .ops = &clk_rcg2_ops,
618 static const struct freq_tbl ftbl_cam_cc_fd_core_clk_src[] = {
619 F(19200000, P_BI_TCXO, 1, 0, 0),
620 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
621 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
622 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
626 static struct clk_rcg2 cam_cc_fd_core_clk_src = {
630 .parent_map = cam_cc_parent_map_0,
631 .freq_tbl = ftbl_cam_cc_fd_core_clk_src,
632 .clkr.hw.init = &(struct clk_init_data){
633 .name = "cam_cc_fd_core_clk_src",
634 .parent_data = cam_cc_parent_data_0,
635 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
636 .flags = CLK_SET_RATE_PARENT,
637 .ops = &clk_rcg2_ops,
641 static struct clk_rcg2 cam_cc_icp_clk_src = {
645 .parent_map = cam_cc_parent_map_0,
646 .freq_tbl = ftbl_cam_cc_fd_core_clk_src,
647 .clkr.hw.init = &(struct clk_init_data){
648 .name = "cam_cc_icp_clk_src",
649 .parent_data = cam_cc_parent_data_0,
650 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
651 .flags = CLK_SET_RATE_PARENT,
652 .ops = &clk_rcg2_ops,
656 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
657 F(19200000, P_BI_TCXO, 1, 0, 0),
658 F(350000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
659 F(475000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
660 F(576000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
661 F(680000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
665 static struct clk_rcg2 cam_cc_ife_0_clk_src = {
669 .parent_map = cam_cc_parent_map_2,
670 .freq_tbl = ftbl_cam_cc_ife_0_clk_src,
671 .clkr.hw.init = &(struct clk_init_data){
672 .name = "cam_cc_ife_0_clk_src",
673 .parent_data = cam_cc_parent_data_2,
674 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
675 .flags = CLK_SET_RATE_PARENT,
676 .ops = &clk_rcg2_ops,
680 static struct clk_regmap_div cam_cc_sbi_div_clk_src = {
684 .clkr.hw.init = &(struct clk_init_data) {
685 .name = "cam_cc_sbi_div_clk_src",
686 .parent_hws = (const struct clk_hw*[]){
687 &cam_cc_ife_0_clk_src.clkr.hw,
690 .flags = CLK_SET_RATE_PARENT,
691 .ops = &clk_regmap_div_ro_ops,
695 static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = {
696 F(19200000, P_BI_TCXO, 1, 0, 0),
697 F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
698 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
702 static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
706 .parent_map = cam_cc_parent_map_0,
707 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
708 .clkr.hw.init = &(struct clk_init_data){
709 .name = "cam_cc_ife_0_csid_clk_src",
710 .parent_data = cam_cc_parent_data_0,
711 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
712 .flags = CLK_SET_RATE_PARENT,
713 .ops = &clk_rcg2_ops,
717 static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
718 F(19200000, P_BI_TCXO, 1, 0, 0),
719 F(350000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
720 F(475000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
721 F(576000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
722 F(680000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
726 static struct clk_rcg2 cam_cc_ife_1_clk_src = {
730 .parent_map = cam_cc_parent_map_3,
731 .freq_tbl = ftbl_cam_cc_ife_1_clk_src,
732 .clkr.hw.init = &(struct clk_init_data){
733 .name = "cam_cc_ife_1_clk_src",
734 .parent_data = cam_cc_parent_data_3,
735 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
736 .flags = CLK_SET_RATE_PARENT,
737 .ops = &clk_rcg2_ops,
741 static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
745 .parent_map = cam_cc_parent_map_0,
746 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
747 .clkr.hw.init = &(struct clk_init_data){
748 .name = "cam_cc_ife_1_csid_clk_src",
749 .parent_data = cam_cc_parent_data_0,
750 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
751 .flags = CLK_SET_RATE_PARENT,
752 .ops = &clk_rcg2_ops,
756 static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = {
757 F(19200000, P_BI_TCXO, 1, 0, 0),
758 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
759 F(480000000, P_CAM_CC_PLL2_OUT_MAIN, 1.5, 0, 0),
763 static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
767 .parent_map = cam_cc_parent_map_0,
768 .freq_tbl = ftbl_cam_cc_ife_lite_clk_src,
769 .clkr.hw.init = &(struct clk_init_data){
770 .name = "cam_cc_ife_lite_clk_src",
771 .parent_data = cam_cc_parent_data_0,
772 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
773 .flags = CLK_SET_RATE_PARENT,
774 .ops = &clk_rcg2_ops,
778 static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
782 .parent_map = cam_cc_parent_map_0,
783 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
784 .clkr.hw.init = &(struct clk_init_data){
785 .name = "cam_cc_ife_lite_csid_clk_src",
786 .parent_data = cam_cc_parent_data_0,
787 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
788 .flags = CLK_SET_RATE_PARENT,
789 .ops = &clk_rcg2_ops,
793 static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = {
794 F(19200000, P_BI_TCXO, 1, 0, 0),
795 F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
796 F(475000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
797 F(525000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
798 F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
802 static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
806 .parent_map = cam_cc_parent_map_4,
807 .freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
808 .clkr.hw.init = &(struct clk_init_data){
809 .name = "cam_cc_ipe_0_clk_src",
810 .parent_data = cam_cc_parent_data_4,
811 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
812 .flags = CLK_SET_RATE_PARENT,
813 .ops = &clk_rcg2_ops,
817 static struct clk_rcg2 cam_cc_jpeg_clk_src = {
821 .parent_map = cam_cc_parent_map_0,
822 .freq_tbl = ftbl_cam_cc_bps_clk_src,
823 .clkr.hw.init = &(struct clk_init_data){
824 .name = "cam_cc_jpeg_clk_src",
825 .parent_data = cam_cc_parent_data_0,
826 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
827 .flags = CLK_SET_RATE_PARENT,
828 .ops = &clk_rcg2_ops,
832 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
833 F(19200000, P_BI_TCXO, 1, 0, 0),
834 F(24000000, P_CAM_CC_PLL2_OUT_EARLY, 10, 1, 6),
835 F(68571429, P_CAM_CC_PLL2_OUT_EARLY, 1, 1, 21),
839 static struct clk_rcg2 cam_cc_mclk0_clk_src = {
843 .parent_map = cam_cc_parent_map_1,
844 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
845 .clkr.hw.init = &(struct clk_init_data){
846 .name = "cam_cc_mclk0_clk_src",
847 .parent_data = cam_cc_parent_data_1,
848 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
849 .flags = CLK_SET_RATE_PARENT,
850 .ops = &clk_rcg2_ops,
854 static struct clk_rcg2 cam_cc_mclk1_clk_src = {
858 .parent_map = cam_cc_parent_map_1,
859 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
860 .clkr.hw.init = &(struct clk_init_data){
861 .name = "cam_cc_mclk1_clk_src",
862 .parent_data = cam_cc_parent_data_1,
863 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
864 .flags = CLK_SET_RATE_PARENT,
865 .ops = &clk_rcg2_ops,
869 static struct clk_rcg2 cam_cc_mclk2_clk_src = {
873 .parent_map = cam_cc_parent_map_1,
874 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
875 .clkr.hw.init = &(struct clk_init_data){
876 .name = "cam_cc_mclk2_clk_src",
877 .parent_data = cam_cc_parent_data_1,
878 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
879 .flags = CLK_SET_RATE_PARENT,
880 .ops = &clk_rcg2_ops,
884 static struct clk_rcg2 cam_cc_mclk3_clk_src = {
888 .parent_map = cam_cc_parent_map_1,
889 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
890 .clkr.hw.init = &(struct clk_init_data){
891 .name = "cam_cc_mclk3_clk_src",
892 .parent_data = cam_cc_parent_data_1,
893 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
894 .flags = CLK_SET_RATE_PARENT,
895 .ops = &clk_rcg2_ops,
899 static struct clk_rcg2 cam_cc_mclk4_clk_src = {
903 .parent_map = cam_cc_parent_map_1,
904 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
905 .clkr.hw.init = &(struct clk_init_data){
906 .name = "cam_cc_mclk4_clk_src",
907 .parent_data = cam_cc_parent_data_1,
908 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
909 .flags = CLK_SET_RATE_PARENT,
910 .ops = &clk_rcg2_ops,
914 static struct clk_rcg2 cam_cc_mclk5_clk_src = {
918 .parent_map = cam_cc_parent_map_1,
919 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
920 .clkr.hw.init = &(struct clk_init_data){
921 .name = "cam_cc_mclk5_clk_src",
922 .parent_data = cam_cc_parent_data_1,
923 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
924 .flags = CLK_SET_RATE_PARENT,
925 .ops = &clk_rcg2_ops,
929 static struct clk_rcg2 cam_cc_mclk6_clk_src = {
933 .parent_map = cam_cc_parent_map_1,
934 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
935 .clkr.hw.init = &(struct clk_init_data){
936 .name = "cam_cc_mclk6_clk_src",
937 .parent_data = cam_cc_parent_data_1,
938 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
939 .flags = CLK_SET_RATE_PARENT,
940 .ops = &clk_rcg2_ops,
944 static struct clk_rcg2 cam_cc_sbi_csid_clk_src = {
948 .parent_map = cam_cc_parent_map_0,
949 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
950 .clkr.hw.init = &(struct clk_init_data){
951 .name = "cam_cc_sbi_csid_clk_src",
952 .parent_data = cam_cc_parent_data_0,
953 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
954 .flags = CLK_SET_RATE_PARENT,
955 .ops = &clk_rcg2_ops,
959 static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
960 F(32768, P_SLEEP_CLK, 1, 0, 0),
964 static struct clk_rcg2 cam_cc_sleep_clk_src = {
968 .parent_map = cam_cc_parent_map_5,
969 .freq_tbl = ftbl_cam_cc_sleep_clk_src,
970 .clkr.hw.init = &(struct clk_init_data){
971 .name = "cam_cc_sleep_clk_src",
972 .parent_data = cam_cc_parent_data_5,
973 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
974 .flags = CLK_SET_RATE_PARENT,
975 .ops = &clk_rcg2_ops,
979 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
980 F(19200000, P_BI_TCXO, 1, 0, 0),
981 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
985 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
989 .parent_map = cam_cc_parent_map_0,
990 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
991 .clkr.hw.init = &(struct clk_init_data){
992 .name = "cam_cc_slow_ahb_clk_src",
993 .parent_data = cam_cc_parent_data_0,
994 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
995 .flags = CLK_SET_RATE_PARENT,
996 .ops = &clk_rcg2_ops,
1000 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
1001 F(19200000, P_BI_TCXO, 1, 0, 0),
1005 static struct clk_rcg2 cam_cc_xo_clk_src = {
1009 .parent_map = cam_cc_parent_map_6,
1010 .freq_tbl = ftbl_cam_cc_xo_clk_src,
1011 .clkr.hw.init = &(struct clk_init_data){
1012 .name = "cam_cc_xo_clk_src",
1013 .parent_data = cam_cc_parent_data_6,
1014 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
1015 .flags = CLK_SET_RATE_PARENT,
1016 .ops = &clk_rcg2_ops,
1020 static struct clk_branch cam_cc_bps_ahb_clk = {
1022 .halt_check = BRANCH_HALT,
1024 .enable_reg = 0x7070,
1025 .enable_mask = BIT(0),
1026 .hw.init = &(struct clk_init_data){
1027 .name = "cam_cc_bps_ahb_clk",
1028 .parent_hws = (const struct clk_hw*[]){
1029 &cam_cc_slow_ahb_clk_src.clkr.hw
1032 .flags = CLK_SET_RATE_PARENT,
1033 .ops = &clk_branch2_ops,
1038 static struct clk_branch cam_cc_bps_areg_clk = {
1040 .halt_check = BRANCH_HALT,
1042 .enable_reg = 0x7054,
1043 .enable_mask = BIT(0),
1044 .hw.init = &(struct clk_init_data){
1045 .name = "cam_cc_bps_areg_clk",
1046 .parent_hws = (const struct clk_hw*[]){
1047 &cam_cc_fast_ahb_clk_src.clkr.hw
1050 .flags = CLK_SET_RATE_PARENT,
1051 .ops = &clk_branch2_ops,
1056 static struct clk_branch cam_cc_bps_axi_clk = {
1058 .halt_check = BRANCH_HALT,
1060 .enable_reg = 0x7038,
1061 .enable_mask = BIT(0),
1062 .hw.init = &(struct clk_init_data){
1063 .name = "cam_cc_bps_axi_clk",
1064 .parent_hws = (const struct clk_hw*[]){
1065 &cam_cc_camnoc_axi_clk_src.clkr.hw
1068 .flags = CLK_SET_RATE_PARENT,
1069 .ops = &clk_branch2_ops,
1074 static struct clk_branch cam_cc_bps_clk = {
1076 .halt_check = BRANCH_HALT,
1078 .enable_reg = 0x7028,
1079 .enable_mask = BIT(0),
1080 .hw.init = &(struct clk_init_data){
1081 .name = "cam_cc_bps_clk",
1082 .parent_hws = (const struct clk_hw*[]){
1083 &cam_cc_bps_clk_src.clkr.hw
1086 .flags = CLK_SET_RATE_PARENT,
1087 .ops = &clk_branch2_ops,
1092 static struct clk_branch cam_cc_camnoc_axi_clk = {
1094 .halt_check = BRANCH_HALT,
1096 .enable_reg = 0xc114,
1097 .enable_mask = BIT(0),
1098 .hw.init = &(struct clk_init_data){
1099 .name = "cam_cc_camnoc_axi_clk",
1100 .parent_hws = (const struct clk_hw*[]){
1101 &cam_cc_camnoc_axi_clk_src.clkr.hw
1104 .flags = CLK_SET_RATE_PARENT,
1105 .ops = &clk_branch2_ops,
1110 static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
1112 .halt_check = BRANCH_HALT,
1114 .enable_reg = 0xc11c,
1115 .enable_mask = BIT(0),
1116 .hw.init = &(struct clk_init_data){
1117 .name = "cam_cc_camnoc_dcd_xo_clk",
1118 .parent_hws = (const struct clk_hw*[]){
1119 &cam_cc_xo_clk_src.clkr.hw
1122 .flags = CLK_SET_RATE_PARENT,
1123 .ops = &clk_branch2_ops,
1128 static struct clk_branch cam_cc_cci_0_clk = {
1130 .halt_check = BRANCH_HALT,
1132 .enable_reg = 0xc0d4,
1133 .enable_mask = BIT(0),
1134 .hw.init = &(struct clk_init_data){
1135 .name = "cam_cc_cci_0_clk",
1136 .parent_hws = (const struct clk_hw*[]){
1137 &cam_cc_cci_0_clk_src.clkr.hw
1140 .flags = CLK_SET_RATE_PARENT,
1141 .ops = &clk_branch2_ops,
1146 static struct clk_branch cam_cc_cci_1_clk = {
1148 .halt_check = BRANCH_HALT,
1150 .enable_reg = 0xc0f0,
1151 .enable_mask = BIT(0),
1152 .hw.init = &(struct clk_init_data){
1153 .name = "cam_cc_cci_1_clk",
1154 .parent_hws = (const struct clk_hw*[]){
1155 &cam_cc_cci_1_clk_src.clkr.hw
1158 .flags = CLK_SET_RATE_PARENT,
1159 .ops = &clk_branch2_ops,
1164 static struct clk_branch cam_cc_core_ahb_clk = {
1166 .halt_check = BRANCH_HALT_DELAY,
1168 .enable_reg = 0xc150,
1169 .enable_mask = BIT(0),
1170 .hw.init = &(struct clk_init_data){
1171 .name = "cam_cc_core_ahb_clk",
1172 .parent_hws = (const struct clk_hw*[]){
1173 &cam_cc_slow_ahb_clk_src.clkr.hw
1176 .flags = CLK_SET_RATE_PARENT,
1177 .ops = &clk_branch2_ops,
1182 static struct clk_branch cam_cc_cpas_ahb_clk = {
1184 .halt_check = BRANCH_HALT,
1186 .enable_reg = 0xc0f4,
1187 .enable_mask = BIT(0),
1188 .hw.init = &(struct clk_init_data){
1189 .name = "cam_cc_cpas_ahb_clk",
1190 .parent_hws = (const struct clk_hw*[]){
1191 &cam_cc_slow_ahb_clk_src.clkr.hw
1194 .flags = CLK_SET_RATE_PARENT,
1195 .ops = &clk_branch2_ops,
1200 static struct clk_branch cam_cc_csi0phytimer_clk = {
1202 .halt_check = BRANCH_HALT,
1204 .enable_reg = 0x6018,
1205 .enable_mask = BIT(0),
1206 .hw.init = &(struct clk_init_data){
1207 .name = "cam_cc_csi0phytimer_clk",
1208 .parent_hws = (const struct clk_hw*[]){
1209 &cam_cc_csi0phytimer_clk_src.clkr.hw
1212 .flags = CLK_SET_RATE_PARENT,
1213 .ops = &clk_branch2_ops,
1218 static struct clk_branch cam_cc_csi1phytimer_clk = {
1220 .halt_check = BRANCH_HALT,
1222 .enable_reg = 0x6038,
1223 .enable_mask = BIT(0),
1224 .hw.init = &(struct clk_init_data){
1225 .name = "cam_cc_csi1phytimer_clk",
1226 .parent_hws = (const struct clk_hw*[]){
1227 &cam_cc_csi1phytimer_clk_src.clkr.hw
1230 .flags = CLK_SET_RATE_PARENT,
1231 .ops = &clk_branch2_ops,
1236 static struct clk_branch cam_cc_csi2phytimer_clk = {
1238 .halt_check = BRANCH_HALT,
1240 .enable_reg = 0x6058,
1241 .enable_mask = BIT(0),
1242 .hw.init = &(struct clk_init_data){
1243 .name = "cam_cc_csi2phytimer_clk",
1244 .parent_hws = (const struct clk_hw*[]){
1245 &cam_cc_csi2phytimer_clk_src.clkr.hw
1248 .flags = CLK_SET_RATE_PARENT,
1249 .ops = &clk_branch2_ops,
1254 static struct clk_branch cam_cc_csi3phytimer_clk = {
1256 .halt_check = BRANCH_HALT,
1258 .enable_reg = 0x6078,
1259 .enable_mask = BIT(0),
1260 .hw.init = &(struct clk_init_data){
1261 .name = "cam_cc_csi3phytimer_clk",
1262 .parent_hws = (const struct clk_hw*[]){
1263 &cam_cc_csi3phytimer_clk_src.clkr.hw
1266 .flags = CLK_SET_RATE_PARENT,
1267 .ops = &clk_branch2_ops,
1272 static struct clk_branch cam_cc_csi4phytimer_clk = {
1274 .halt_check = BRANCH_HALT,
1276 .enable_reg = 0x6098,
1277 .enable_mask = BIT(0),
1278 .hw.init = &(struct clk_init_data){
1279 .name = "cam_cc_csi4phytimer_clk",
1280 .parent_hws = (const struct clk_hw*[]){
1281 &cam_cc_csi4phytimer_clk_src.clkr.hw
1284 .flags = CLK_SET_RATE_PARENT,
1285 .ops = &clk_branch2_ops,
1290 static struct clk_branch cam_cc_csi5phytimer_clk = {
1292 .halt_check = BRANCH_HALT,
1294 .enable_reg = 0x60b8,
1295 .enable_mask = BIT(0),
1296 .hw.init = &(struct clk_init_data){
1297 .name = "cam_cc_csi5phytimer_clk",
1298 .parent_hws = (const struct clk_hw*[]){
1299 &cam_cc_csi5phytimer_clk_src.clkr.hw
1302 .flags = CLK_SET_RATE_PARENT,
1303 .ops = &clk_branch2_ops,
1308 static struct clk_branch cam_cc_csiphy0_clk = {
1310 .halt_check = BRANCH_HALT,
1312 .enable_reg = 0x601c,
1313 .enable_mask = BIT(0),
1314 .hw.init = &(struct clk_init_data){
1315 .name = "cam_cc_csiphy0_clk",
1316 .parent_hws = (const struct clk_hw*[]){
1317 &cam_cc_cphy_rx_clk_src.clkr.hw
1320 .flags = CLK_SET_RATE_PARENT,
1321 .ops = &clk_branch2_ops,
1326 static struct clk_branch cam_cc_csiphy1_clk = {
1328 .halt_check = BRANCH_HALT,
1330 .enable_reg = 0x603c,
1331 .enable_mask = BIT(0),
1332 .hw.init = &(struct clk_init_data){
1333 .name = "cam_cc_csiphy1_clk",
1334 .parent_hws = (const struct clk_hw*[]){
1335 &cam_cc_cphy_rx_clk_src.clkr.hw
1338 .flags = CLK_SET_RATE_PARENT,
1339 .ops = &clk_branch2_ops,
1344 static struct clk_branch cam_cc_csiphy2_clk = {
1346 .halt_check = BRANCH_HALT,
1348 .enable_reg = 0x605c,
1349 .enable_mask = BIT(0),
1350 .hw.init = &(struct clk_init_data){
1351 .name = "cam_cc_csiphy2_clk",
1352 .parent_hws = (const struct clk_hw*[]){
1353 &cam_cc_cphy_rx_clk_src.clkr.hw
1356 .flags = CLK_SET_RATE_PARENT,
1357 .ops = &clk_branch2_ops,
1362 static struct clk_branch cam_cc_csiphy3_clk = {
1364 .halt_check = BRANCH_HALT,
1366 .enable_reg = 0x607c,
1367 .enable_mask = BIT(0),
1368 .hw.init = &(struct clk_init_data){
1369 .name = "cam_cc_csiphy3_clk",
1370 .parent_hws = (const struct clk_hw*[]){
1371 &cam_cc_cphy_rx_clk_src.clkr.hw
1374 .flags = CLK_SET_RATE_PARENT,
1375 .ops = &clk_branch2_ops,
1380 static struct clk_branch cam_cc_csiphy4_clk = {
1382 .halt_check = BRANCH_HALT,
1384 .enable_reg = 0x609c,
1385 .enable_mask = BIT(0),
1386 .hw.init = &(struct clk_init_data){
1387 .name = "cam_cc_csiphy4_clk",
1388 .parent_hws = (const struct clk_hw*[]){
1389 &cam_cc_cphy_rx_clk_src.clkr.hw
1392 .flags = CLK_SET_RATE_PARENT,
1393 .ops = &clk_branch2_ops,
1398 static struct clk_branch cam_cc_csiphy5_clk = {
1400 .halt_check = BRANCH_HALT,
1402 .enable_reg = 0x60bc,
1403 .enable_mask = BIT(0),
1404 .hw.init = &(struct clk_init_data){
1405 .name = "cam_cc_csiphy5_clk",
1406 .parent_hws = (const struct clk_hw*[]){
1407 &cam_cc_cphy_rx_clk_src.clkr.hw
1410 .flags = CLK_SET_RATE_PARENT,
1411 .ops = &clk_branch2_ops,
1416 static struct clk_branch cam_cc_fd_core_clk = {
1418 .halt_check = BRANCH_HALT,
1420 .enable_reg = 0xc0b0,
1421 .enable_mask = BIT(0),
1422 .hw.init = &(struct clk_init_data){
1423 .name = "cam_cc_fd_core_clk",
1424 .parent_hws = (const struct clk_hw*[]){
1425 &cam_cc_fd_core_clk_src.clkr.hw
1428 .flags = CLK_SET_RATE_PARENT,
1429 .ops = &clk_branch2_ops,
1434 static struct clk_branch cam_cc_fd_core_uar_clk = {
1436 .halt_check = BRANCH_HALT,
1438 .enable_reg = 0xc0b8,
1439 .enable_mask = BIT(0),
1440 .hw.init = &(struct clk_init_data){
1441 .name = "cam_cc_fd_core_uar_clk",
1442 .parent_hws = (const struct clk_hw*[]){
1443 &cam_cc_fd_core_clk_src.clkr.hw
1446 .flags = CLK_SET_RATE_PARENT,
1447 .ops = &clk_branch2_ops,
1452 static struct clk_branch cam_cc_gdsc_clk = {
1454 .halt_check = BRANCH_HALT,
1456 .enable_reg = 0xc16c,
1457 .enable_mask = BIT(0),
1458 .hw.init = &(struct clk_init_data){
1459 .name = "cam_cc_gdsc_clk",
1460 .parent_hws = (const struct clk_hw*[]){
1461 &cam_cc_xo_clk_src.clkr.hw
1464 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1465 .ops = &clk_branch2_ops,
1470 static struct clk_branch cam_cc_icp_ahb_clk = {
1472 .halt_check = BRANCH_HALT,
1474 .enable_reg = 0xc094,
1475 .enable_mask = BIT(0),
1476 .hw.init = &(struct clk_init_data){
1477 .name = "cam_cc_icp_ahb_clk",
1478 .parent_hws = (const struct clk_hw*[]){
1479 &cam_cc_slow_ahb_clk_src.clkr.hw
1482 .flags = CLK_SET_RATE_PARENT,
1483 .ops = &clk_branch2_ops,
1488 static struct clk_branch cam_cc_icp_clk = {
1490 .halt_check = BRANCH_HALT,
1492 .enable_reg = 0xc08c,
1493 .enable_mask = BIT(0),
1494 .hw.init = &(struct clk_init_data){
1495 .name = "cam_cc_icp_clk",
1496 .parent_hws = (const struct clk_hw*[]){
1497 &cam_cc_icp_clk_src.clkr.hw
1500 .flags = CLK_SET_RATE_PARENT,
1501 .ops = &clk_branch2_ops,
1506 static struct clk_branch cam_cc_ife_0_ahb_clk = {
1508 .halt_check = BRANCH_HALT,
1510 .enable_reg = 0xa088,
1511 .enable_mask = BIT(0),
1512 .hw.init = &(struct clk_init_data){
1513 .name = "cam_cc_ife_0_ahb_clk",
1514 .parent_hws = (const struct clk_hw*[]){
1515 &cam_cc_slow_ahb_clk_src.clkr.hw
1518 .flags = CLK_SET_RATE_PARENT,
1519 .ops = &clk_branch2_ops,
1524 static struct clk_branch cam_cc_ife_0_areg_clk = {
1526 .halt_check = BRANCH_HALT,
1528 .enable_reg = 0xa030,
1529 .enable_mask = BIT(0),
1530 .hw.init = &(struct clk_init_data){
1531 .name = "cam_cc_ife_0_areg_clk",
1532 .parent_hws = (const struct clk_hw*[]){
1533 &cam_cc_fast_ahb_clk_src.clkr.hw
1536 .flags = CLK_SET_RATE_PARENT,
1537 .ops = &clk_branch2_ops,
1542 static struct clk_branch cam_cc_ife_0_axi_clk = {
1544 .halt_check = BRANCH_HALT,
1546 .enable_reg = 0xa084,
1547 .enable_mask = BIT(0),
1548 .hw.init = &(struct clk_init_data){
1549 .name = "cam_cc_ife_0_axi_clk",
1550 .parent_hws = (const struct clk_hw*[]){
1551 &cam_cc_camnoc_axi_clk_src.clkr.hw
1554 .flags = CLK_SET_RATE_PARENT,
1555 .ops = &clk_branch2_ops,
1560 static struct clk_branch cam_cc_ife_0_clk = {
1562 .halt_check = BRANCH_HALT,
1564 .enable_reg = 0xa028,
1565 .enable_mask = BIT(0),
1566 .hw.init = &(struct clk_init_data){
1567 .name = "cam_cc_ife_0_clk",
1568 .parent_hws = (const struct clk_hw*[]){
1569 &cam_cc_ife_0_clk_src.clkr.hw
1572 .flags = CLK_SET_RATE_PARENT,
1573 .ops = &clk_branch2_ops,
1578 static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
1580 .halt_check = BRANCH_HALT,
1582 .enable_reg = 0xa080,
1583 .enable_mask = BIT(0),
1584 .hw.init = &(struct clk_init_data){
1585 .name = "cam_cc_ife_0_cphy_rx_clk",
1586 .parent_hws = (const struct clk_hw*[]){
1587 &cam_cc_cphy_rx_clk_src.clkr.hw
1590 .flags = CLK_SET_RATE_PARENT,
1591 .ops = &clk_branch2_ops,
1596 static struct clk_branch cam_cc_ife_0_csid_clk = {
1598 .halt_check = BRANCH_HALT,
1600 .enable_reg = 0xa058,
1601 .enable_mask = BIT(0),
1602 .hw.init = &(struct clk_init_data){
1603 .name = "cam_cc_ife_0_csid_clk",
1604 .parent_hws = (const struct clk_hw*[]){
1605 &cam_cc_ife_0_csid_clk_src.clkr.hw
1608 .flags = CLK_SET_RATE_PARENT,
1609 .ops = &clk_branch2_ops,
1614 static struct clk_branch cam_cc_ife_0_dsp_clk = {
1616 .halt_check = BRANCH_HALT,
1618 .enable_reg = 0xa03c,
1619 .enable_mask = BIT(0),
1620 .hw.init = &(struct clk_init_data){
1621 .name = "cam_cc_ife_0_dsp_clk",
1622 .parent_hws = (const struct clk_hw*[]){
1623 &cam_cc_ife_0_clk_src.clkr.hw
1626 .flags = CLK_SET_RATE_PARENT,
1627 .ops = &clk_branch2_ops,
1632 static struct clk_branch cam_cc_ife_1_ahb_clk = {
1634 .halt_check = BRANCH_HALT,
1636 .enable_reg = 0xb068,
1637 .enable_mask = BIT(0),
1638 .hw.init = &(struct clk_init_data){
1639 .name = "cam_cc_ife_1_ahb_clk",
1640 .parent_hws = (const struct clk_hw*[]){
1641 &cam_cc_slow_ahb_clk_src.clkr.hw
1644 .flags = CLK_SET_RATE_PARENT,
1645 .ops = &clk_branch2_ops,
1650 static struct clk_branch cam_cc_ife_1_areg_clk = {
1652 .halt_check = BRANCH_HALT,
1654 .enable_reg = 0xb030,
1655 .enable_mask = BIT(0),
1656 .hw.init = &(struct clk_init_data){
1657 .name = "cam_cc_ife_1_areg_clk",
1658 .parent_hws = (const struct clk_hw*[]){
1659 &cam_cc_fast_ahb_clk_src.clkr.hw
1662 .flags = CLK_SET_RATE_PARENT,
1663 .ops = &clk_branch2_ops,
1668 static struct clk_branch cam_cc_ife_1_axi_clk = {
1670 .halt_check = BRANCH_HALT,
1672 .enable_reg = 0xb064,
1673 .enable_mask = BIT(0),
1674 .hw.init = &(struct clk_init_data){
1675 .name = "cam_cc_ife_1_axi_clk",
1676 .parent_hws = (const struct clk_hw*[]){
1677 &cam_cc_camnoc_axi_clk_src.clkr.hw
1680 .flags = CLK_SET_RATE_PARENT,
1681 .ops = &clk_branch2_ops,
1686 static struct clk_branch cam_cc_ife_1_clk = {
1688 .halt_check = BRANCH_HALT,
1690 .enable_reg = 0xb028,
1691 .enable_mask = BIT(0),
1692 .hw.init = &(struct clk_init_data){
1693 .name = "cam_cc_ife_1_clk",
1694 .parent_hws = (const struct clk_hw*[]){
1695 &cam_cc_ife_1_clk_src.clkr.hw
1698 .flags = CLK_SET_RATE_PARENT,
1699 .ops = &clk_branch2_ops,
1704 static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
1706 .halt_check = BRANCH_HALT,
1708 .enable_reg = 0xb060,
1709 .enable_mask = BIT(0),
1710 .hw.init = &(struct clk_init_data){
1711 .name = "cam_cc_ife_1_cphy_rx_clk",
1712 .parent_hws = (const struct clk_hw*[]){
1713 &cam_cc_cphy_rx_clk_src.clkr.hw
1716 .flags = CLK_SET_RATE_PARENT,
1717 .ops = &clk_branch2_ops,
1722 static struct clk_branch cam_cc_ife_1_csid_clk = {
1724 .halt_check = BRANCH_HALT,
1726 .enable_reg = 0xb058,
1727 .enable_mask = BIT(0),
1728 .hw.init = &(struct clk_init_data){
1729 .name = "cam_cc_ife_1_csid_clk",
1730 .parent_hws = (const struct clk_hw*[]){
1731 &cam_cc_ife_1_csid_clk_src.clkr.hw
1734 .flags = CLK_SET_RATE_PARENT,
1735 .ops = &clk_branch2_ops,
1740 static struct clk_branch cam_cc_ife_1_dsp_clk = {
1742 .halt_check = BRANCH_HALT,
1744 .enable_reg = 0xb03c,
1745 .enable_mask = BIT(0),
1746 .hw.init = &(struct clk_init_data){
1747 .name = "cam_cc_ife_1_dsp_clk",
1748 .parent_hws = (const struct clk_hw*[]){
1749 &cam_cc_ife_1_clk_src.clkr.hw
1752 .flags = CLK_SET_RATE_PARENT,
1753 .ops = &clk_branch2_ops,
1758 static struct clk_branch cam_cc_ife_lite_ahb_clk = {
1760 .halt_check = BRANCH_HALT,
1762 .enable_reg = 0xc040,
1763 .enable_mask = BIT(0),
1764 .hw.init = &(struct clk_init_data){
1765 .name = "cam_cc_ife_lite_ahb_clk",
1766 .parent_hws = (const struct clk_hw*[]){
1767 &cam_cc_slow_ahb_clk_src.clkr.hw
1770 .flags = CLK_SET_RATE_PARENT,
1771 .ops = &clk_branch2_ops,
1776 static struct clk_branch cam_cc_ife_lite_axi_clk = {
1778 .halt_check = BRANCH_HALT,
1780 .enable_reg = 0xc044,
1781 .enable_mask = BIT(0),
1782 .hw.init = &(struct clk_init_data){
1783 .name = "cam_cc_ife_lite_axi_clk",
1784 .parent_hws = (const struct clk_hw*[]){
1785 &cam_cc_camnoc_axi_clk_src.clkr.hw
1788 .flags = CLK_SET_RATE_PARENT,
1789 .ops = &clk_branch2_ops,
1794 static struct clk_branch cam_cc_ife_lite_clk = {
1796 .halt_check = BRANCH_HALT,
1798 .enable_reg = 0xc018,
1799 .enable_mask = BIT(0),
1800 .hw.init = &(struct clk_init_data){
1801 .name = "cam_cc_ife_lite_clk",
1802 .parent_hws = (const struct clk_hw*[]){
1803 &cam_cc_ife_lite_clk_src.clkr.hw
1806 .flags = CLK_SET_RATE_PARENT,
1807 .ops = &clk_branch2_ops,
1812 static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
1814 .halt_check = BRANCH_HALT,
1816 .enable_reg = 0xc03c,
1817 .enable_mask = BIT(0),
1818 .hw.init = &(struct clk_init_data){
1819 .name = "cam_cc_ife_lite_cphy_rx_clk",
1820 .parent_hws = (const struct clk_hw*[]){
1821 &cam_cc_cphy_rx_clk_src.clkr.hw
1824 .flags = CLK_SET_RATE_PARENT,
1825 .ops = &clk_branch2_ops,
1830 static struct clk_branch cam_cc_ife_lite_csid_clk = {
1832 .halt_check = BRANCH_HALT,
1834 .enable_reg = 0xc034,
1835 .enable_mask = BIT(0),
1836 .hw.init = &(struct clk_init_data){
1837 .name = "cam_cc_ife_lite_csid_clk",
1838 .parent_hws = (const struct clk_hw*[]){
1839 &cam_cc_ife_lite_csid_clk_src.clkr.hw
1842 .flags = CLK_SET_RATE_PARENT,
1843 .ops = &clk_branch2_ops,
1848 static struct clk_branch cam_cc_ipe_0_ahb_clk = {
1850 .halt_check = BRANCH_HALT,
1852 .enable_reg = 0x8040,
1853 .enable_mask = BIT(0),
1854 .hw.init = &(struct clk_init_data){
1855 .name = "cam_cc_ipe_0_ahb_clk",
1856 .parent_hws = (const struct clk_hw*[]){
1857 &cam_cc_slow_ahb_clk_src.clkr.hw
1860 .flags = CLK_SET_RATE_PARENT,
1861 .ops = &clk_branch2_ops,
1866 static struct clk_branch cam_cc_ipe_0_areg_clk = {
1868 .halt_check = BRANCH_HALT,
1870 .enable_reg = 0x803c,
1871 .enable_mask = BIT(0),
1872 .hw.init = &(struct clk_init_data){
1873 .name = "cam_cc_ipe_0_areg_clk",
1874 .parent_hws = (const struct clk_hw*[]){
1875 &cam_cc_fast_ahb_clk_src.clkr.hw
1878 .flags = CLK_SET_RATE_PARENT,
1879 .ops = &clk_branch2_ops,
1884 static struct clk_branch cam_cc_ipe_0_axi_clk = {
1886 .halt_check = BRANCH_HALT,
1888 .enable_reg = 0x8038,
1889 .enable_mask = BIT(0),
1890 .hw.init = &(struct clk_init_data){
1891 .name = "cam_cc_ipe_0_axi_clk",
1892 .parent_hws = (const struct clk_hw*[]){
1893 &cam_cc_camnoc_axi_clk_src.clkr.hw
1896 .flags = CLK_SET_RATE_PARENT,
1897 .ops = &clk_branch2_ops,
1902 static struct clk_branch cam_cc_ipe_0_clk = {
1904 .halt_check = BRANCH_HALT,
1906 .enable_reg = 0x8028,
1907 .enable_mask = BIT(0),
1908 .hw.init = &(struct clk_init_data){
1909 .name = "cam_cc_ipe_0_clk",
1910 .parent_hws = (const struct clk_hw*[]){
1911 &cam_cc_ipe_0_clk_src.clkr.hw
1914 .flags = CLK_SET_RATE_PARENT,
1915 .ops = &clk_branch2_ops,
1920 static struct clk_branch cam_cc_jpeg_clk = {
1922 .halt_check = BRANCH_HALT,
1924 .enable_reg = 0xc060,
1925 .enable_mask = BIT(0),
1926 .hw.init = &(struct clk_init_data){
1927 .name = "cam_cc_jpeg_clk",
1928 .parent_hws = (const struct clk_hw*[]){
1929 &cam_cc_jpeg_clk_src.clkr.hw
1932 .flags = CLK_SET_RATE_PARENT,
1933 .ops = &clk_branch2_ops,
1938 static struct clk_branch cam_cc_mclk0_clk = {
1940 .halt_check = BRANCH_HALT,
1942 .enable_reg = 0x5018,
1943 .enable_mask = BIT(0),
1944 .hw.init = &(struct clk_init_data){
1945 .name = "cam_cc_mclk0_clk",
1946 .parent_hws = (const struct clk_hw*[]){
1947 &cam_cc_mclk0_clk_src.clkr.hw
1950 .flags = CLK_SET_RATE_PARENT,
1951 .ops = &clk_branch2_ops,
1956 static struct clk_branch cam_cc_mclk1_clk = {
1958 .halt_check = BRANCH_HALT,
1960 .enable_reg = 0x5034,
1961 .enable_mask = BIT(0),
1962 .hw.init = &(struct clk_init_data){
1963 .name = "cam_cc_mclk1_clk",
1964 .parent_hws = (const struct clk_hw*[]){
1965 &cam_cc_mclk1_clk_src.clkr.hw
1968 .flags = CLK_SET_RATE_PARENT,
1969 .ops = &clk_branch2_ops,
1974 static struct clk_branch cam_cc_mclk2_clk = {
1976 .halt_check = BRANCH_HALT,
1978 .enable_reg = 0x5050,
1979 .enable_mask = BIT(0),
1980 .hw.init = &(struct clk_init_data){
1981 .name = "cam_cc_mclk2_clk",
1982 .parent_hws = (const struct clk_hw*[]){
1983 &cam_cc_mclk2_clk_src.clkr.hw
1986 .flags = CLK_SET_RATE_PARENT,
1987 .ops = &clk_branch2_ops,
1992 static struct clk_branch cam_cc_mclk3_clk = {
1994 .halt_check = BRANCH_HALT,
1996 .enable_reg = 0x506c,
1997 .enable_mask = BIT(0),
1998 .hw.init = &(struct clk_init_data){
1999 .name = "cam_cc_mclk3_clk",
2000 .parent_hws = (const struct clk_hw*[]){
2001 &cam_cc_mclk3_clk_src.clkr.hw
2004 .flags = CLK_SET_RATE_PARENT,
2005 .ops = &clk_branch2_ops,
2010 static struct clk_branch cam_cc_mclk4_clk = {
2012 .halt_check = BRANCH_HALT,
2014 .enable_reg = 0x5088,
2015 .enable_mask = BIT(0),
2016 .hw.init = &(struct clk_init_data){
2017 .name = "cam_cc_mclk4_clk",
2018 .parent_hws = (const struct clk_hw*[]){
2019 &cam_cc_mclk4_clk_src.clkr.hw
2022 .flags = CLK_SET_RATE_PARENT,
2023 .ops = &clk_branch2_ops,
2028 static struct clk_branch cam_cc_mclk5_clk = {
2030 .halt_check = BRANCH_HALT,
2032 .enable_reg = 0x50a4,
2033 .enable_mask = BIT(0),
2034 .hw.init = &(struct clk_init_data){
2035 .name = "cam_cc_mclk5_clk",
2036 .parent_hws = (const struct clk_hw*[]){
2037 &cam_cc_mclk5_clk_src.clkr.hw
2040 .flags = CLK_SET_RATE_PARENT,
2041 .ops = &clk_branch2_ops,
2046 static struct clk_branch cam_cc_mclk6_clk = {
2048 .halt_check = BRANCH_HALT,
2050 .enable_reg = 0x50c0,
2051 .enable_mask = BIT(0),
2052 .hw.init = &(struct clk_init_data){
2053 .name = "cam_cc_mclk6_clk",
2054 .parent_hws = (const struct clk_hw*[]){
2055 &cam_cc_mclk6_clk_src.clkr.hw
2058 .flags = CLK_SET_RATE_PARENT,
2059 .ops = &clk_branch2_ops,
2064 static struct clk_branch cam_cc_sbi_ahb_clk = {
2066 .halt_check = BRANCH_HALT,
2068 .enable_reg = 0x9040,
2069 .enable_mask = BIT(0),
2070 .hw.init = &(struct clk_init_data){
2071 .name = "cam_cc_sbi_ahb_clk",
2072 .parent_hws = (const struct clk_hw*[]){
2073 &cam_cc_slow_ahb_clk_src.clkr.hw
2076 .flags = CLK_SET_RATE_PARENT,
2077 .ops = &clk_branch2_ops,
2082 static struct clk_branch cam_cc_sbi_axi_clk = {
2084 .halt_check = BRANCH_HALT,
2086 .enable_reg = 0x903c,
2087 .enable_mask = BIT(0),
2088 .hw.init = &(struct clk_init_data){
2089 .name = "cam_cc_sbi_axi_clk",
2090 .parent_hws = (const struct clk_hw*[]){
2091 &cam_cc_camnoc_axi_clk_src.clkr.hw
2094 .flags = CLK_SET_RATE_PARENT,
2095 .ops = &clk_branch2_ops,
2100 static struct clk_branch cam_cc_sbi_clk = {
2102 .halt_check = BRANCH_HALT,
2104 .enable_reg = 0x9014,
2105 .enable_mask = BIT(0),
2106 .hw.init = &(struct clk_init_data){
2107 .name = "cam_cc_sbi_clk",
2108 .parent_hws = (const struct clk_hw*[]){
2109 &cam_cc_sbi_div_clk_src.clkr.hw
2112 .flags = CLK_SET_RATE_PARENT,
2113 .ops = &clk_branch2_ops,
2118 static struct clk_branch cam_cc_sbi_cphy_rx_clk = {
2120 .halt_check = BRANCH_HALT,
2122 .enable_reg = 0x9038,
2123 .enable_mask = BIT(0),
2124 .hw.init = &(struct clk_init_data){
2125 .name = "cam_cc_sbi_cphy_rx_clk",
2126 .parent_hws = (const struct clk_hw*[]){
2127 &cam_cc_cphy_rx_clk_src.clkr.hw
2130 .flags = CLK_SET_RATE_PARENT,
2131 .ops = &clk_branch2_ops,
2136 static struct clk_branch cam_cc_sbi_csid_clk = {
2138 .halt_check = BRANCH_HALT,
2140 .enable_reg = 0x9034,
2141 .enable_mask = BIT(0),
2142 .hw.init = &(struct clk_init_data){
2143 .name = "cam_cc_sbi_csid_clk",
2144 .parent_hws = (const struct clk_hw*[]){
2145 &cam_cc_sbi_csid_clk_src.clkr.hw
2148 .flags = CLK_SET_RATE_PARENT,
2149 .ops = &clk_branch2_ops,
2154 static struct clk_branch cam_cc_sbi_ife_0_clk = {
2156 .halt_check = BRANCH_HALT,
2158 .enable_reg = 0x9044,
2159 .enable_mask = BIT(0),
2160 .hw.init = &(struct clk_init_data){
2161 .name = "cam_cc_sbi_ife_0_clk",
2162 .parent_hws = (const struct clk_hw*[]){
2163 &cam_cc_ife_0_clk_src.clkr.hw
2166 .flags = CLK_SET_RATE_PARENT,
2167 .ops = &clk_branch2_ops,
2172 static struct clk_branch cam_cc_sbi_ife_1_clk = {
2174 .halt_check = BRANCH_HALT,
2176 .enable_reg = 0x9048,
2177 .enable_mask = BIT(0),
2178 .hw.init = &(struct clk_init_data){
2179 .name = "cam_cc_sbi_ife_1_clk",
2180 .parent_hws = (const struct clk_hw*[]){
2181 &cam_cc_ife_1_clk_src.clkr.hw
2184 .flags = CLK_SET_RATE_PARENT,
2185 .ops = &clk_branch2_ops,
2190 static struct clk_branch cam_cc_sleep_clk = {
2192 .halt_check = BRANCH_HALT,
2194 .enable_reg = 0xc188,
2195 .enable_mask = BIT(0),
2196 .hw.init = &(struct clk_init_data){
2197 .name = "cam_cc_sleep_clk",
2198 .parent_hws = (const struct clk_hw*[]){
2199 &cam_cc_sleep_clk_src.clkr.hw
2202 .flags = CLK_SET_RATE_PARENT,
2203 .ops = &clk_branch2_ops,
2208 static struct gdsc titan_top_gdsc;
2210 static struct gdsc bps_gdsc = {
2215 .flags = HW_CTRL | POLL_CFG_GDSCR,
2216 .pwrsts = PWRSTS_OFF_ON,
2219 static struct gdsc ipe_0_gdsc = {
2222 .name = "ipe_0_gdsc",
2224 .flags = HW_CTRL | POLL_CFG_GDSCR,
2225 .pwrsts = PWRSTS_OFF_ON,
2228 static struct gdsc sbi_gdsc = {
2233 .flags = HW_CTRL | POLL_CFG_GDSCR,
2234 .pwrsts = PWRSTS_OFF_ON,
2237 static struct gdsc ife_0_gdsc = {
2240 .name = "ife_0_gdsc",
2242 .flags = POLL_CFG_GDSCR,
2243 .parent = &titan_top_gdsc.pd,
2244 .pwrsts = PWRSTS_OFF_ON,
2247 static struct gdsc ife_1_gdsc = {
2250 .name = "ife_1_gdsc",
2252 .flags = POLL_CFG_GDSCR,
2253 .parent = &titan_top_gdsc.pd,
2254 .pwrsts = PWRSTS_OFF_ON,
2257 static struct gdsc titan_top_gdsc = {
2260 .name = "titan_top_gdsc",
2262 .flags = POLL_CFG_GDSCR,
2263 .pwrsts = PWRSTS_OFF_ON,
2266 static struct clk_regmap *cam_cc_sm8250_clocks[] = {
2267 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
2268 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr,
2269 [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr,
2270 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
2271 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
2272 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
2273 [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
2274 [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
2275 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
2276 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
2277 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
2278 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
2279 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
2280 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
2281 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
2282 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
2283 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
2284 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
2285 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
2286 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
2287 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
2288 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
2289 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
2290 [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
2291 [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
2292 [CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr,
2293 [CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr,
2294 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
2295 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
2296 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
2297 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
2298 [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
2299 [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr,
2300 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
2301 [CAM_CC_FD_CORE_CLK] = &cam_cc_fd_core_clk.clkr,
2302 [CAM_CC_FD_CORE_CLK_SRC] = &cam_cc_fd_core_clk_src.clkr,
2303 [CAM_CC_FD_CORE_UAR_CLK] = &cam_cc_fd_core_uar_clk.clkr,
2304 [CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr,
2305 [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
2306 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
2307 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
2308 [CAM_CC_IFE_0_AHB_CLK] = &cam_cc_ife_0_ahb_clk.clkr,
2309 [CAM_CC_IFE_0_AREG_CLK] = &cam_cc_ife_0_areg_clk.clkr,
2310 [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr,
2311 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
2312 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
2313 [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr,
2314 [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr,
2315 [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr,
2316 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
2317 [CAM_CC_IFE_1_AHB_CLK] = &cam_cc_ife_1_ahb_clk.clkr,
2318 [CAM_CC_IFE_1_AREG_CLK] = &cam_cc_ife_1_areg_clk.clkr,
2319 [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr,
2320 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
2321 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
2322 [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr,
2323 [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr,
2324 [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr,
2325 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
2326 [CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr,
2327 [CAM_CC_IFE_LITE_AXI_CLK] = &cam_cc_ife_lite_axi_clk.clkr,
2328 [CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
2329 [CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
2330 [CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
2331 [CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
2332 [CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
2333 [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr,
2334 [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr,
2335 [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr,
2336 [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr,
2337 [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr,
2338 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
2339 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
2340 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
2341 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
2342 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
2343 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
2344 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
2345 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
2346 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
2347 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
2348 [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
2349 [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
2350 [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
2351 [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
2352 [CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr,
2353 [CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr,
2354 [CAM_CC_PLL0] = &cam_cc_pll0.clkr,
2355 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
2356 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
2357 [CAM_CC_PLL1] = &cam_cc_pll1.clkr,
2358 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
2359 [CAM_CC_PLL2] = &cam_cc_pll2.clkr,
2360 [CAM_CC_PLL2_OUT_MAIN] = &cam_cc_pll2_out_main.clkr,
2361 [CAM_CC_PLL3] = &cam_cc_pll3.clkr,
2362 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
2363 [CAM_CC_PLL4] = &cam_cc_pll4.clkr,
2364 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
2365 [CAM_CC_SBI_AHB_CLK] = &cam_cc_sbi_ahb_clk.clkr,
2366 [CAM_CC_SBI_AXI_CLK] = &cam_cc_sbi_axi_clk.clkr,
2367 [CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr,
2368 [CAM_CC_SBI_CPHY_RX_CLK] = &cam_cc_sbi_cphy_rx_clk.clkr,
2369 [CAM_CC_SBI_CSID_CLK] = &cam_cc_sbi_csid_clk.clkr,
2370 [CAM_CC_SBI_CSID_CLK_SRC] = &cam_cc_sbi_csid_clk_src.clkr,
2371 [CAM_CC_SBI_DIV_CLK_SRC] = &cam_cc_sbi_div_clk_src.clkr,
2372 [CAM_CC_SBI_IFE_0_CLK] = &cam_cc_sbi_ife_0_clk.clkr,
2373 [CAM_CC_SBI_IFE_1_CLK] = &cam_cc_sbi_ife_1_clk.clkr,
2374 [CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr,
2375 [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
2376 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
2377 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
2380 static struct gdsc *cam_cc_sm8250_gdscs[] = {
2381 [BPS_GDSC] = &bps_gdsc,
2382 [IPE_0_GDSC] = &ipe_0_gdsc,
2383 [SBI_GDSC] = &sbi_gdsc,
2384 [IFE_0_GDSC] = &ife_0_gdsc,
2385 [IFE_1_GDSC] = &ife_1_gdsc,
2386 [TITAN_TOP_GDSC] = &titan_top_gdsc,
2389 static const struct qcom_reset_map cam_cc_sm8250_resets[] = {
2390 [CAM_CC_BPS_BCR] = { 0x7000 },
2391 [CAM_CC_ICP_BCR] = { 0xc070 },
2392 [CAM_CC_IFE_0_BCR] = { 0xa000 },
2393 [CAM_CC_IFE_1_BCR] = { 0xb000 },
2394 [CAM_CC_IPE_0_BCR] = { 0x8000 },
2395 [CAM_CC_SBI_BCR] = { 0x9000 },
2398 static const struct regmap_config cam_cc_sm8250_regmap_config = {
2402 .max_register = 0xe004,
2406 static const struct qcom_cc_desc cam_cc_sm8250_desc = {
2407 .config = &cam_cc_sm8250_regmap_config,
2408 .clks = cam_cc_sm8250_clocks,
2409 .num_clks = ARRAY_SIZE(cam_cc_sm8250_clocks),
2410 .resets = cam_cc_sm8250_resets,
2411 .num_resets = ARRAY_SIZE(cam_cc_sm8250_resets),
2412 .gdscs = cam_cc_sm8250_gdscs,
2413 .num_gdscs = ARRAY_SIZE(cam_cc_sm8250_gdscs),
2416 static const struct of_device_id cam_cc_sm8250_match_table[] = {
2417 { .compatible = "qcom,sm8250-camcc" },
2420 MODULE_DEVICE_TABLE(of, cam_cc_sm8250_match_table);
2422 static int cam_cc_sm8250_probe(struct platform_device *pdev)
2424 struct regmap *regmap;
2426 regmap = qcom_cc_map(pdev, &cam_cc_sm8250_desc);
2428 return PTR_ERR(regmap);
2430 clk_lucid_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
2431 clk_lucid_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
2432 clk_zonda_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
2433 clk_lucid_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
2434 clk_lucid_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
2436 return qcom_cc_really_probe(pdev, &cam_cc_sm8250_desc, regmap);
2439 static struct platform_driver cam_cc_sm8250_driver = {
2440 .probe = cam_cc_sm8250_probe,
2442 .name = "cam_cc-sm8250",
2443 .of_match_table = cam_cc_sm8250_match_table,
2447 module_platform_driver(cam_cc_sm8250_driver);
2449 MODULE_DESCRIPTION("QTI CAMCC SM8250 Driver");
2450 MODULE_LICENSE("GPL v2");