1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
6 #include <linux/clk-provider.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
14 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
16 #include "clk-alpha-pll.h"
17 #include "clk-branch.h"
25 P_CAM_CC_PLL0_OUT_EVEN,
26 P_CAM_CC_PLL0_OUT_MAIN,
27 P_CAM_CC_PLL0_OUT_ODD,
28 P_CAM_CC_PLL1_OUT_EVEN,
29 P_CAM_CC_PLL2_OUT_AUX2,
30 P_CAM_CC_PLL2_OUT_EARLY,
31 P_CAM_CC_PLL3_OUT_EVEN,
32 P_CAM_CC_PLL4_OUT_EVEN,
33 P_CAM_CC_PLL5_OUT_EVEN,
34 P_CAM_CC_PLL6_OUT_EVEN,
35 P_CAM_CC_PLL6_OUT_MAIN,
36 P_CAM_CC_PLL6_OUT_ODD,
40 static struct pll_vco lucid_vco[] = {
41 { 249600000, 2000000000, 0 },
44 static struct pll_vco zonda_vco[] = {
45 { 595200000UL, 3600000000UL, 0 },
48 /* 1200MHz Configuration */
49 static const struct alpha_pll_config cam_cc_pll0_config = {
52 .config_ctl_val = 0x20485699,
53 .config_ctl_hi_val = 0x00002261,
54 .config_ctl_hi1_val = 0x329A299C,
55 .user_ctl_val = 0x00003101,
56 .user_ctl_hi_val = 0x00000805,
57 .user_ctl_hi1_val = 0x00000000,
60 static struct clk_alpha_pll cam_cc_pll0 = {
62 .vco_table = lucid_vco,
63 .num_vco = ARRAY_SIZE(lucid_vco),
64 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
66 .hw.init = &(struct clk_init_data){
67 .name = "cam_cc_pll0",
68 .parent_data = &(const struct clk_parent_data){
72 .ops = &clk_alpha_pll_lucid_ops,
77 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
82 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
85 .post_div_table = post_div_table_cam_cc_pll0_out_even,
86 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
88 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
89 .clkr.hw.init = &(struct clk_init_data){
90 .name = "cam_cc_pll0_out_even",
91 .parent_hws = (const struct clk_hw*[]) {
95 .flags = CLK_SET_RATE_PARENT,
96 .ops = &clk_alpha_pll_postdiv_lucid_ops,
100 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
105 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
107 .post_div_shift = 12,
108 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
109 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
111 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
112 .clkr.hw.init = &(struct clk_init_data){
113 .name = "cam_cc_pll0_out_odd",
114 .parent_hws = (const struct clk_hw*[]) {
115 &cam_cc_pll0.clkr.hw,
118 .flags = CLK_SET_RATE_PARENT,
119 .ops = &clk_alpha_pll_postdiv_lucid_ops,
123 /* 600MHz Configuration */
124 static const struct alpha_pll_config cam_cc_pll1_config = {
127 .config_ctl_val = 0x20485699,
128 .config_ctl_hi_val = 0x00002261,
129 .config_ctl_hi1_val = 0x329A299C,
130 .user_ctl_val = 0x00000101,
131 .user_ctl_hi_val = 0x00000805,
132 .user_ctl_hi1_val = 0x00000000,
135 static struct clk_alpha_pll cam_cc_pll1 = {
137 .vco_table = lucid_vco,
138 .num_vco = ARRAY_SIZE(lucid_vco),
139 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
141 .hw.init = &(struct clk_init_data){
142 .name = "cam_cc_pll1",
143 .parent_data = &(const struct clk_parent_data){
144 .fw_name = "bi_tcxo",
147 .ops = &clk_alpha_pll_lucid_ops,
152 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
157 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
160 .post_div_table = post_div_table_cam_cc_pll1_out_even,
161 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
163 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
164 .clkr.hw.init = &(struct clk_init_data){
165 .name = "cam_cc_pll1_out_even",
166 .parent_hws = (const struct clk_hw*[]) {
167 &cam_cc_pll1.clkr.hw,
170 .flags = CLK_SET_RATE_PARENT,
171 .ops = &clk_alpha_pll_postdiv_lucid_ops,
175 /* 1440MHz Configuration */
176 static const struct alpha_pll_config cam_cc_pll2_config = {
179 .config_ctl_val = 0x08200800,
180 .config_ctl_hi_val = 0x05022011,
181 .config_ctl_hi1_val = 0x08000000,
182 .user_ctl_val = 0x00000301,
185 static struct clk_alpha_pll cam_cc_pll2 = {
187 .vco_table = zonda_vco,
188 .num_vco = ARRAY_SIZE(zonda_vco),
189 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
191 .hw.init = &(struct clk_init_data){
192 .name = "cam_cc_pll2",
193 .parent_data = &(const struct clk_parent_data){
194 .fw_name = "bi_tcxo",
197 .ops = &clk_alpha_pll_zonda_ops,
202 static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux[] = {
207 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = {
210 .post_div_table = post_div_table_cam_cc_pll2_out_aux,
211 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux),
213 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
214 .clkr.hw.init = &(struct clk_init_data){
215 .name = "cam_cc_pll2_out_aux",
216 .parent_hws = (const struct clk_hw*[]) {
217 &cam_cc_pll2.clkr.hw,
220 .flags = CLK_SET_RATE_PARENT,
221 .ops = &clk_alpha_pll_postdiv_zonda_ops,
225 static const struct clk_div_table post_div_table_cam_cc_pll2_out_aux2[] = {
230 static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux2 = {
233 .post_div_table = post_div_table_cam_cc_pll2_out_aux2,
234 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll2_out_aux2),
236 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_ZONDA],
237 .clkr.hw.init = &(struct clk_init_data){
238 .name = "cam_cc_pll2_out_aux2",
239 .parent_hws = (const struct clk_hw*[]) {
240 &cam_cc_pll2.clkr.hw,
243 .flags = CLK_SET_RATE_PARENT,
244 .ops = &clk_alpha_pll_postdiv_zonda_ops,
248 /* 760MHz Configuration */
249 static const struct alpha_pll_config cam_cc_pll3_config = {
252 .config_ctl_val = 0x20485699,
253 .config_ctl_hi_val = 0x00002261,
254 .config_ctl_hi1_val = 0x329A299C,
255 .user_ctl_val = 0x00000101,
256 .user_ctl_hi_val = 0x00000805,
257 .user_ctl_hi1_val = 0x00000000,
260 static struct clk_alpha_pll cam_cc_pll3 = {
262 .vco_table = lucid_vco,
263 .num_vco = ARRAY_SIZE(lucid_vco),
264 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
266 .hw.init = &(struct clk_init_data){
267 .name = "cam_cc_pll3",
268 .parent_data = &(const struct clk_parent_data){
269 .fw_name = "bi_tcxo",
272 .ops = &clk_alpha_pll_lucid_ops,
277 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
282 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
285 .post_div_table = post_div_table_cam_cc_pll3_out_even,
286 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
288 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
289 .clkr.hw.init = &(struct clk_init_data){
290 .name = "cam_cc_pll3_out_even",
291 .parent_hws = (const struct clk_hw*[]) {
292 &cam_cc_pll3.clkr.hw,
295 .flags = CLK_SET_RATE_PARENT,
296 .ops = &clk_alpha_pll_postdiv_lucid_ops,
300 /* 760MHz Configuration */
301 static const struct alpha_pll_config cam_cc_pll4_config = {
304 .config_ctl_val = 0x20485699,
305 .config_ctl_hi_val = 0x00002261,
306 .config_ctl_hi1_val = 0x329A299C,
307 .user_ctl_val = 0x00000101,
308 .user_ctl_hi_val = 0x00000805,
309 .user_ctl_hi1_val = 0x00000000,
312 static struct clk_alpha_pll cam_cc_pll4 = {
314 .vco_table = lucid_vco,
315 .num_vco = ARRAY_SIZE(lucid_vco),
316 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
318 .hw.init = &(struct clk_init_data){
319 .name = "cam_cc_pll4",
320 .parent_data = &(const struct clk_parent_data){
321 .fw_name = "bi_tcxo",
324 .ops = &clk_alpha_pll_lucid_ops,
329 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
334 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
337 .post_div_table = post_div_table_cam_cc_pll4_out_even,
338 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
340 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
341 .clkr.hw.init = &(struct clk_init_data){
342 .name = "cam_cc_pll4_out_even",
343 .parent_hws = (const struct clk_hw*[]) {
344 &cam_cc_pll4.clkr.hw,
347 .flags = CLK_SET_RATE_PARENT,
348 .ops = &clk_alpha_pll_postdiv_lucid_ops,
352 /* 760MHz Configuration */
353 static const struct alpha_pll_config cam_cc_pll5_config = {
356 .config_ctl_val = 0x20485699,
357 .config_ctl_hi_val = 0x00002261,
358 .config_ctl_hi1_val = 0x329A299C,
359 .user_ctl_val = 0x00000101,
360 .user_ctl_hi_val = 0x00000805,
361 .user_ctl_hi1_val = 0x00000000,
364 static struct clk_alpha_pll cam_cc_pll5 = {
366 .vco_table = lucid_vco,
367 .num_vco = ARRAY_SIZE(lucid_vco),
368 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
370 .hw.init = &(struct clk_init_data){
371 .name = "cam_cc_pll5",
372 .parent_data = &(const struct clk_parent_data){
373 .fw_name = "bi_tcxo",
376 .ops = &clk_alpha_pll_lucid_ops,
381 static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
386 static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
389 .post_div_table = post_div_table_cam_cc_pll5_out_even,
390 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even),
392 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
393 .clkr.hw.init = &(struct clk_init_data){
394 .name = "cam_cc_pll5_out_even",
395 .parent_hws = (const struct clk_hw*[]) {
396 &cam_cc_pll5.clkr.hw,
399 .flags = CLK_SET_RATE_PARENT,
400 .ops = &clk_alpha_pll_postdiv_lucid_ops,
404 /* 960MHz Configuration */
405 static const struct alpha_pll_config cam_cc_pll6_config = {
408 .config_ctl_val = 0x20485699,
409 .config_ctl_hi_val = 0x00002261,
410 .config_ctl_hi1_val = 0x329A299C,
411 .user_ctl_val = 0x00003101,
412 .user_ctl_hi_val = 0x00000805,
413 .user_ctl_hi1_val = 0x00000000,
416 static struct clk_alpha_pll cam_cc_pll6 = {
418 .vco_table = lucid_vco,
419 .num_vco = ARRAY_SIZE(lucid_vco),
420 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
422 .hw.init = &(struct clk_init_data){
423 .name = "cam_cc_pll6",
424 .parent_data = &(const struct clk_parent_data){
425 .fw_name = "bi_tcxo",
428 .ops = &clk_alpha_pll_lucid_ops,
433 static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = {
438 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
441 .post_div_table = post_div_table_cam_cc_pll6_out_even,
442 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even),
444 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
445 .clkr.hw.init = &(struct clk_init_data){
446 .name = "cam_cc_pll6_out_even",
447 .parent_hws = (const struct clk_hw*[]) {
448 &cam_cc_pll6.clkr.hw,
451 .flags = CLK_SET_RATE_PARENT,
452 .ops = &clk_alpha_pll_postdiv_lucid_ops,
456 static const struct clk_div_table post_div_table_cam_cc_pll6_out_odd[] = {
461 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_odd = {
463 .post_div_shift = 12,
464 .post_div_table = post_div_table_cam_cc_pll6_out_odd,
465 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_odd),
467 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
468 .clkr.hw.init = &(struct clk_init_data){
469 .name = "cam_cc_pll6_out_odd",
470 .parent_hws = (const struct clk_hw*[]) {
471 &cam_cc_pll6.clkr.hw,
474 .flags = CLK_SET_RATE_PARENT,
475 .ops = &clk_alpha_pll_postdiv_lucid_ops,
479 static const struct parent_map cam_cc_parent_map_0[] = {
481 { P_CAM_CC_PLL0_OUT_MAIN, 1 },
482 { P_CAM_CC_PLL0_OUT_EVEN, 2 },
483 { P_CAM_CC_PLL0_OUT_ODD, 3 },
484 { P_CAM_CC_PLL6_OUT_EVEN, 5 },
487 static const struct clk_parent_data cam_cc_parent_data_0[] = {
488 { .fw_name = "bi_tcxo" },
489 { .hw = &cam_cc_pll0.clkr.hw },
490 { .hw = &cam_cc_pll0_out_even.clkr.hw },
491 { .hw = &cam_cc_pll0_out_odd.clkr.hw },
492 { .hw = &cam_cc_pll6_out_even.clkr.hw },
495 static const struct parent_map cam_cc_parent_map_1[] = {
497 { P_CAM_CC_PLL0_OUT_MAIN, 1 },
498 { P_CAM_CC_PLL0_OUT_EVEN, 2 },
499 { P_CAM_CC_PLL0_OUT_ODD, 3 },
500 { P_CAM_CC_PLL6_OUT_MAIN, 4 },
501 { P_CAM_CC_PLL6_OUT_EVEN, 5 },
504 static const struct clk_parent_data cam_cc_parent_data_1[] = {
505 { .fw_name = "bi_tcxo" },
506 { .hw = &cam_cc_pll0.clkr.hw },
507 { .hw = &cam_cc_pll0_out_even.clkr.hw },
508 { .hw = &cam_cc_pll0_out_odd.clkr.hw },
509 { .hw = &cam_cc_pll6.clkr.hw },
510 { .hw = &cam_cc_pll6_out_even.clkr.hw },
513 static const struct parent_map cam_cc_parent_map_2[] = {
515 { P_CAM_CC_PLL2_OUT_AUX2, 3 },
516 { P_CAM_CC_PLL2_OUT_EARLY, 5 },
519 static const struct clk_parent_data cam_cc_parent_data_2[] = {
520 { .fw_name = "bi_tcxo" },
521 { .hw = &cam_cc_pll2_out_aux2.clkr.hw },
522 { .hw = &cam_cc_pll2.clkr.hw },
525 static const struct parent_map cam_cc_parent_map_3[] = {
527 { P_CAM_CC_PLL0_OUT_MAIN, 1 },
528 { P_CAM_CC_PLL0_OUT_EVEN, 2 },
529 { P_CAM_CC_PLL0_OUT_ODD, 3 },
530 { P_CAM_CC_PLL6_OUT_EVEN, 5 },
531 { P_CAM_CC_PLL6_OUT_ODD, 6 },
534 static const struct clk_parent_data cam_cc_parent_data_3[] = {
535 { .fw_name = "bi_tcxo" },
536 { .hw = &cam_cc_pll0.clkr.hw },
537 { .hw = &cam_cc_pll0_out_even.clkr.hw },
538 { .hw = &cam_cc_pll0_out_odd.clkr.hw },
539 { .hw = &cam_cc_pll6_out_even.clkr.hw },
540 { .hw = &cam_cc_pll6_out_odd.clkr.hw },
543 static const struct parent_map cam_cc_parent_map_4[] = {
545 { P_CAM_CC_PLL3_OUT_EVEN, 6 },
548 static const struct clk_parent_data cam_cc_parent_data_4[] = {
549 { .fw_name = "bi_tcxo" },
550 { .hw = &cam_cc_pll3_out_even.clkr.hw },
553 static const struct parent_map cam_cc_parent_map_5[] = {
555 { P_CAM_CC_PLL4_OUT_EVEN, 6 },
558 static const struct clk_parent_data cam_cc_parent_data_5[] = {
559 { .fw_name = "bi_tcxo" },
560 { .hw = &cam_cc_pll4_out_even.clkr.hw },
563 static const struct parent_map cam_cc_parent_map_6[] = {
565 { P_CAM_CC_PLL5_OUT_EVEN, 6 },
568 static const struct clk_parent_data cam_cc_parent_data_6[] = {
569 { .fw_name = "bi_tcxo" },
570 { .hw = &cam_cc_pll5_out_even.clkr.hw },
573 static const struct parent_map cam_cc_parent_map_7[] = {
575 { P_CAM_CC_PLL1_OUT_EVEN, 4 },
578 static const struct clk_parent_data cam_cc_parent_data_7[] = {
579 { .fw_name = "bi_tcxo" },
580 { .hw = &cam_cc_pll1_out_even.clkr.hw },
583 static const struct parent_map cam_cc_parent_map_8[] = {
587 static const struct clk_parent_data cam_cc_parent_data_8[] = {
588 { .fw_name = "sleep_clk" },
591 static const struct parent_map cam_cc_parent_map_9[] = {
595 static const struct clk_parent_data cam_cc_parent_data_9_ao[] = {
596 { .fw_name = "bi_tcxo_ao" },
599 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
600 F(19200000, P_BI_TCXO, 1, 0, 0),
601 F(100000000, P_CAM_CC_PLL0_OUT_ODD, 4, 0, 0),
602 F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
603 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
604 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
605 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
609 static struct clk_rcg2 cam_cc_bps_clk_src = {
613 .parent_map = cam_cc_parent_map_0,
614 .freq_tbl = ftbl_cam_cc_bps_clk_src,
615 .clkr.hw.init = &(struct clk_init_data){
616 .name = "cam_cc_bps_clk_src",
617 .parent_data = cam_cc_parent_data_0,
618 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
619 .ops = &clk_rcg2_shared_ops,
623 static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
624 F(19200000, P_BI_TCXO, 1, 0, 0),
625 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
626 F(240000000, P_CAM_CC_PLL6_OUT_EVEN, 2, 0, 0),
627 F(320000000, P_CAM_CC_PLL6_OUT_ODD, 1, 0, 0),
628 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
629 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
633 static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
637 .parent_map = cam_cc_parent_map_3,
638 .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
639 .clkr.hw.init = &(struct clk_init_data){
640 .name = "cam_cc_camnoc_axi_clk_src",
641 .parent_data = cam_cc_parent_data_3,
642 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
643 .ops = &clk_rcg2_shared_ops,
647 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
648 F(19200000, P_BI_TCXO, 1, 0, 0),
649 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
653 static struct clk_rcg2 cam_cc_cci_0_clk_src = {
657 .parent_map = cam_cc_parent_map_0,
658 .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
659 .clkr.hw.init = &(struct clk_init_data){
660 .name = "cam_cc_cci_0_clk_src",
661 .parent_data = cam_cc_parent_data_0,
662 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
663 .ops = &clk_rcg2_shared_ops,
667 static struct clk_rcg2 cam_cc_cci_1_clk_src = {
671 .parent_map = cam_cc_parent_map_0,
672 .freq_tbl = ftbl_cam_cc_cci_0_clk_src,
673 .clkr.hw.init = &(struct clk_init_data){
674 .name = "cam_cc_cci_1_clk_src",
675 .parent_data = cam_cc_parent_data_0,
676 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
677 .ops = &clk_rcg2_shared_ops,
681 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
682 F(19200000, P_BI_TCXO, 1, 0, 0),
683 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
684 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
688 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
692 .parent_map = cam_cc_parent_map_1,
693 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
694 .clkr.hw.init = &(struct clk_init_data){
695 .name = "cam_cc_cphy_rx_clk_src",
696 .parent_data = cam_cc_parent_data_1,
697 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
698 .ops = &clk_rcg2_shared_ops,
702 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
703 F(19200000, P_BI_TCXO, 1, 0, 0),
704 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
708 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
712 .parent_map = cam_cc_parent_map_0,
713 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
714 .clkr.hw.init = &(struct clk_init_data){
715 .name = "cam_cc_csi0phytimer_clk_src",
716 .parent_data = cam_cc_parent_data_0,
717 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
718 .ops = &clk_rcg2_shared_ops,
722 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
726 .parent_map = cam_cc_parent_map_0,
727 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
728 .clkr.hw.init = &(struct clk_init_data){
729 .name = "cam_cc_csi1phytimer_clk_src",
730 .parent_data = cam_cc_parent_data_0,
731 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
732 .ops = &clk_rcg2_shared_ops,
736 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
740 .parent_map = cam_cc_parent_map_0,
741 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
742 .clkr.hw.init = &(struct clk_init_data){
743 .name = "cam_cc_csi2phytimer_clk_src",
744 .parent_data = cam_cc_parent_data_0,
745 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
746 .ops = &clk_rcg2_shared_ops,
750 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
754 .parent_map = cam_cc_parent_map_0,
755 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
756 .clkr.hw.init = &(struct clk_init_data){
757 .name = "cam_cc_csi3phytimer_clk_src",
758 .parent_data = cam_cc_parent_data_0,
759 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
760 .ops = &clk_rcg2_shared_ops,
764 static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
768 .parent_map = cam_cc_parent_map_0,
769 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
770 .clkr.hw.init = &(struct clk_init_data){
771 .name = "cam_cc_csi4phytimer_clk_src",
772 .parent_data = cam_cc_parent_data_0,
773 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
774 .ops = &clk_rcg2_shared_ops,
778 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
779 F(19200000, P_BI_TCXO, 1, 0, 0),
780 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0),
781 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
782 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
783 F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
784 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
788 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
792 .parent_map = cam_cc_parent_map_0,
793 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
794 .clkr.hw.init = &(struct clk_init_data){
795 .name = "cam_cc_fast_ahb_clk_src",
796 .parent_data = cam_cc_parent_data_0,
797 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
798 .ops = &clk_rcg2_shared_ops,
802 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
803 F(19200000, P_BI_TCXO, 1, 0, 0),
804 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
805 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
806 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
810 static struct clk_rcg2 cam_cc_icp_clk_src = {
814 .parent_map = cam_cc_parent_map_0,
815 .freq_tbl = ftbl_cam_cc_icp_clk_src,
816 .clkr.hw.init = &(struct clk_init_data){
817 .name = "cam_cc_icp_clk_src",
818 .parent_data = cam_cc_parent_data_0,
819 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
820 .ops = &clk_rcg2_shared_ops,
824 static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
825 F(19200000, P_BI_TCXO, 1, 0, 0),
826 F(380000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
827 F(510000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
828 F(637000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
829 F(760000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
833 static struct clk_rcg2 cam_cc_ife_0_clk_src = {
837 .parent_map = cam_cc_parent_map_4,
838 .freq_tbl = ftbl_cam_cc_ife_0_clk_src,
839 .clkr.hw.init = &(struct clk_init_data){
840 .name = "cam_cc_ife_0_clk_src",
841 .parent_data = cam_cc_parent_data_4,
842 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
843 .flags = CLK_SET_RATE_PARENT,
844 .ops = &clk_rcg2_shared_ops,
848 static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
849 F(19200000, P_BI_TCXO, 1, 0, 0),
850 F(380000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
851 F(510000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
852 F(637000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
853 F(760000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
857 static struct clk_rcg2 cam_cc_ife_1_clk_src = {
861 .parent_map = cam_cc_parent_map_5,
862 .freq_tbl = ftbl_cam_cc_ife_1_clk_src,
863 .clkr.hw.init = &(struct clk_init_data){
864 .name = "cam_cc_ife_1_clk_src",
865 .parent_data = cam_cc_parent_data_5,
866 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
867 .flags = CLK_SET_RATE_PARENT,
868 .ops = &clk_rcg2_shared_ops,
872 static const struct freq_tbl ftbl_cam_cc_ife_0_csid_clk_src[] = {
873 F(19200000, P_BI_TCXO, 1, 0, 0),
874 F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
875 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
876 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0),
880 static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
884 .parent_map = cam_cc_parent_map_1,
885 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
886 .clkr.hw.init = &(struct clk_init_data){
887 .name = "cam_cc_ife_0_csid_clk_src",
888 .parent_data = cam_cc_parent_data_1,
889 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
890 .ops = &clk_rcg2_shared_ops,
894 static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
898 .parent_map = cam_cc_parent_map_1,
899 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
900 .clkr.hw.init = &(struct clk_init_data){
901 .name = "cam_cc_ife_1_csid_clk_src",
902 .parent_data = cam_cc_parent_data_1,
903 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
904 .ops = &clk_rcg2_shared_ops,
908 static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = {
909 F(19200000, P_BI_TCXO, 1, 0, 0),
910 F(380000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
911 F(510000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
912 F(637000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
913 F(760000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
917 static struct clk_rcg2 cam_cc_ife_2_clk_src = {
921 .parent_map = cam_cc_parent_map_6,
922 .freq_tbl = ftbl_cam_cc_ife_2_clk_src,
923 .clkr.hw.init = &(struct clk_init_data){
924 .name = "cam_cc_ife_2_clk_src",
925 .parent_data = cam_cc_parent_data_6,
926 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
927 .flags = CLK_SET_RATE_PARENT,
928 .ops = &clk_rcg2_shared_ops,
932 static struct clk_rcg2 cam_cc_ife_2_csid_clk_src = {
936 .parent_map = cam_cc_parent_map_1,
937 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
938 .clkr.hw.init = &(struct clk_init_data){
939 .name = "cam_cc_ife_2_csid_clk_src",
940 .parent_data = cam_cc_parent_data_1,
941 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
942 .ops = &clk_rcg2_shared_ops,
946 static const struct freq_tbl ftbl_cam_cc_ife_lite_0_clk_src[] = {
947 F(19200000, P_BI_TCXO, 1, 0, 0),
948 F(320000000, P_CAM_CC_PLL6_OUT_ODD, 1, 0, 0),
949 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
950 F(480000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
951 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
955 static struct clk_rcg2 cam_cc_ife_lite_0_clk_src = {
959 .parent_map = cam_cc_parent_map_3,
960 .freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src,
961 .clkr.hw.init = &(struct clk_init_data){
962 .name = "cam_cc_ife_lite_0_clk_src",
963 .parent_data = cam_cc_parent_data_3,
964 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
965 .ops = &clk_rcg2_shared_ops,
969 static struct clk_rcg2 cam_cc_ife_lite_0_csid_clk_src = {
973 .parent_map = cam_cc_parent_map_1,
974 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
975 .clkr.hw.init = &(struct clk_init_data){
976 .name = "cam_cc_ife_lite_0_csid_clk_src",
977 .parent_data = cam_cc_parent_data_1,
978 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
979 .ops = &clk_rcg2_shared_ops,
983 static struct clk_rcg2 cam_cc_ife_lite_1_clk_src = {
987 .parent_map = cam_cc_parent_map_3,
988 .freq_tbl = ftbl_cam_cc_ife_lite_0_clk_src,
989 .clkr.hw.init = &(struct clk_init_data){
990 .name = "cam_cc_ife_lite_1_clk_src",
991 .parent_data = cam_cc_parent_data_3,
992 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
993 .ops = &clk_rcg2_shared_ops,
997 static struct clk_rcg2 cam_cc_ife_lite_1_csid_clk_src = {
1001 .parent_map = cam_cc_parent_map_1,
1002 .freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
1003 .clkr.hw.init = &(struct clk_init_data){
1004 .name = "cam_cc_ife_lite_1_csid_clk_src",
1005 .parent_data = cam_cc_parent_data_1,
1006 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1007 .ops = &clk_rcg2_shared_ops,
1011 static const struct freq_tbl ftbl_cam_cc_ipe_0_clk_src[] = {
1012 F(19200000, P_BI_TCXO, 1, 0, 0),
1013 F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1014 F(430000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1015 F(520000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1016 F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
1020 static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
1024 .parent_map = cam_cc_parent_map_7,
1025 .freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
1026 .clkr.hw.init = &(struct clk_init_data){
1027 .name = "cam_cc_ipe_0_clk_src",
1028 .parent_data = cam_cc_parent_data_7,
1029 .num_parents = ARRAY_SIZE(cam_cc_parent_data_7),
1030 .flags = CLK_SET_RATE_PARENT,
1031 .ops = &clk_rcg2_shared_ops,
1035 static struct clk_rcg2 cam_cc_jpeg_clk_src = {
1039 .parent_map = cam_cc_parent_map_0,
1040 .freq_tbl = ftbl_cam_cc_bps_clk_src,
1041 .clkr.hw.init = &(struct clk_init_data){
1042 .name = "cam_cc_jpeg_clk_src",
1043 .parent_data = cam_cc_parent_data_0,
1044 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1045 .ops = &clk_rcg2_shared_ops,
1049 static const struct freq_tbl ftbl_cam_cc_lrme_clk_src[] = {
1050 F(19200000, P_BI_TCXO, 1, 0, 0),
1051 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
1052 F(240000000, P_CAM_CC_PLL6_OUT_EVEN, 2, 0, 0),
1053 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
1054 F(320000000, P_CAM_CC_PLL6_OUT_ODD, 1, 0, 0),
1055 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
1059 static struct clk_rcg2 cam_cc_lrme_clk_src = {
1063 .parent_map = cam_cc_parent_map_3,
1064 .freq_tbl = ftbl_cam_cc_lrme_clk_src,
1065 .clkr.hw.init = &(struct clk_init_data){
1066 .name = "cam_cc_lrme_clk_src",
1067 .parent_data = cam_cc_parent_data_3,
1068 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
1069 .ops = &clk_rcg2_shared_ops,
1073 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
1074 F(19200000, P_CAM_CC_PLL2_OUT_EARLY, 1, 1, 75),
1075 F(24000000, P_CAM_CC_PLL2_OUT_EARLY, 10, 1, 6),
1076 F(34285714, P_CAM_CC_PLL2_OUT_EARLY, 2, 1, 21),
1080 static struct clk_rcg2 cam_cc_mclk0_clk_src = {
1084 .parent_map = cam_cc_parent_map_2,
1085 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1086 .clkr.hw.init = &(struct clk_init_data){
1087 .name = "cam_cc_mclk0_clk_src",
1088 .parent_data = cam_cc_parent_data_2,
1089 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
1090 .ops = &clk_rcg2_shared_ops,
1094 static struct clk_rcg2 cam_cc_mclk1_clk_src = {
1098 .parent_map = cam_cc_parent_map_2,
1099 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1100 .clkr.hw.init = &(struct clk_init_data){
1101 .name = "cam_cc_mclk1_clk_src",
1102 .parent_data = cam_cc_parent_data_2,
1103 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
1104 .ops = &clk_rcg2_shared_ops,
1108 static struct clk_rcg2 cam_cc_mclk2_clk_src = {
1112 .parent_map = cam_cc_parent_map_2,
1113 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1114 .clkr.hw.init = &(struct clk_init_data){
1115 .name = "cam_cc_mclk2_clk_src",
1116 .parent_data = cam_cc_parent_data_2,
1117 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
1118 .ops = &clk_rcg2_shared_ops,
1122 static struct clk_rcg2 cam_cc_mclk3_clk_src = {
1126 .parent_map = cam_cc_parent_map_2,
1127 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1128 .clkr.hw.init = &(struct clk_init_data){
1129 .name = "cam_cc_mclk3_clk_src",
1130 .parent_data = cam_cc_parent_data_2,
1131 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
1132 .ops = &clk_rcg2_shared_ops,
1136 static struct clk_rcg2 cam_cc_mclk4_clk_src = {
1140 .parent_map = cam_cc_parent_map_2,
1141 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1142 .clkr.hw.init = &(struct clk_init_data){
1143 .name = "cam_cc_mclk4_clk_src",
1144 .parent_data = cam_cc_parent_data_2,
1145 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
1146 .ops = &clk_rcg2_shared_ops,
1150 static struct clk_rcg2 cam_cc_mclk5_clk_src = {
1154 .parent_map = cam_cc_parent_map_2,
1155 .freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1156 .clkr.hw.init = &(struct clk_init_data){
1157 .name = "cam_cc_mclk5_clk_src",
1158 .parent_data = cam_cc_parent_data_2,
1159 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
1160 .ops = &clk_rcg2_shared_ops,
1164 static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
1165 F(32000, P_SLEEP_CLK, 1, 0, 0),
1169 static struct clk_rcg2 cam_cc_sleep_clk_src = {
1173 .parent_map = cam_cc_parent_map_8,
1174 .freq_tbl = ftbl_cam_cc_sleep_clk_src,
1175 .clkr.hw.init = &(struct clk_init_data){
1176 .name = "cam_cc_sleep_clk_src",
1177 .parent_data = cam_cc_parent_data_8,
1178 .num_parents = ARRAY_SIZE(cam_cc_parent_data_8),
1179 .ops = &clk_rcg2_ops,
1183 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
1184 F(19200000, P_BI_TCXO, 1, 0, 0),
1185 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
1189 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
1193 .parent_map = cam_cc_parent_map_0,
1194 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
1195 .clkr.hw.init = &(struct clk_init_data){
1196 .name = "cam_cc_slow_ahb_clk_src",
1197 .parent_data = cam_cc_parent_data_0,
1198 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1199 .ops = &clk_rcg2_shared_ops,
1203 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
1204 F(19200000, P_BI_TCXO, 1, 0, 0),
1208 static struct clk_rcg2 cam_cc_xo_clk_src = {
1212 .parent_map = cam_cc_parent_map_9,
1213 .freq_tbl = ftbl_cam_cc_xo_clk_src,
1214 .clkr.hw.init = &(struct clk_init_data){
1215 .name = "cam_cc_xo_clk_src",
1216 .parent_data = cam_cc_parent_data_9_ao,
1217 .num_parents = ARRAY_SIZE(cam_cc_parent_data_9_ao),
1218 .ops = &clk_rcg2_ops,
1222 static struct clk_branch cam_cc_bps_ahb_clk = {
1224 .halt_check = BRANCH_HALT,
1226 .enable_reg = 0x7070,
1227 .enable_mask = BIT(0),
1228 .hw.init = &(struct clk_init_data){
1229 .name = "cam_cc_bps_ahb_clk",
1230 .parent_hws = (const struct clk_hw*[]) {
1231 &cam_cc_slow_ahb_clk_src.clkr.hw,
1234 .flags = CLK_SET_RATE_PARENT,
1235 .ops = &clk_branch2_ops,
1240 static struct clk_branch cam_cc_bps_areg_clk = {
1242 .halt_check = BRANCH_HALT,
1244 .enable_reg = 0x7054,
1245 .enable_mask = BIT(0),
1246 .hw.init = &(struct clk_init_data){
1247 .name = "cam_cc_bps_areg_clk",
1248 .parent_hws = (const struct clk_hw*[]) {
1249 &cam_cc_fast_ahb_clk_src.clkr.hw,
1252 .flags = CLK_SET_RATE_PARENT,
1253 .ops = &clk_branch2_ops,
1258 static struct clk_branch cam_cc_bps_axi_clk = {
1260 .halt_check = BRANCH_HALT,
1262 .enable_reg = 0x7038,
1263 .enable_mask = BIT(0),
1264 .hw.init = &(struct clk_init_data){
1265 .name = "cam_cc_bps_axi_clk",
1266 .parent_hws = (const struct clk_hw*[]) {
1267 &cam_cc_camnoc_axi_clk_src.clkr.hw,
1270 .flags = CLK_SET_RATE_PARENT,
1271 .ops = &clk_branch2_ops,
1276 static struct clk_branch cam_cc_bps_clk = {
1278 .halt_check = BRANCH_HALT,
1280 .enable_reg = 0x7028,
1281 .enable_mask = BIT(0),
1282 .hw.init = &(struct clk_init_data){
1283 .name = "cam_cc_bps_clk",
1284 .parent_hws = (const struct clk_hw*[]) {
1285 &cam_cc_bps_clk_src.clkr.hw,
1288 .flags = CLK_SET_RATE_PARENT,
1289 .ops = &clk_branch2_ops,
1294 static struct clk_branch cam_cc_camnoc_axi_clk = {
1296 .halt_check = BRANCH_HALT,
1298 .enable_reg = 0xc140,
1299 .enable_mask = BIT(0),
1300 .hw.init = &(struct clk_init_data){
1301 .name = "cam_cc_camnoc_axi_clk",
1302 .parent_hws = (const struct clk_hw*[]) {
1303 &cam_cc_camnoc_axi_clk_src.clkr.hw,
1306 .flags = CLK_SET_RATE_PARENT,
1307 .ops = &clk_branch2_ops,
1312 static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
1314 .halt_check = BRANCH_HALT,
1316 .enable_reg = 0xc148,
1317 .enable_mask = BIT(0),
1318 .hw.init = &(struct clk_init_data){
1319 .name = "cam_cc_camnoc_dcd_xo_clk",
1320 .parent_hws = (const struct clk_hw*[]) {
1321 &cam_cc_xo_clk_src.clkr.hw,
1324 .flags = CLK_SET_RATE_PARENT,
1325 .ops = &clk_branch2_ops,
1330 static struct clk_branch cam_cc_cci_0_clk = {
1332 .halt_check = BRANCH_HALT,
1334 .enable_reg = 0xc0f8,
1335 .enable_mask = BIT(0),
1336 .hw.init = &(struct clk_init_data){
1337 .name = "cam_cc_cci_0_clk",
1338 .parent_hws = (const struct clk_hw*[]) {
1339 &cam_cc_cci_0_clk_src.clkr.hw,
1342 .flags = CLK_SET_RATE_PARENT,
1343 .ops = &clk_branch2_ops,
1348 static struct clk_branch cam_cc_cci_1_clk = {
1350 .halt_check = BRANCH_HALT,
1352 .enable_reg = 0xc114,
1353 .enable_mask = BIT(0),
1354 .hw.init = &(struct clk_init_data){
1355 .name = "cam_cc_cci_1_clk",
1356 .parent_hws = (const struct clk_hw*[]) {
1357 &cam_cc_cci_1_clk_src.clkr.hw,
1360 .flags = CLK_SET_RATE_PARENT,
1361 .ops = &clk_branch2_ops,
1366 static struct clk_branch cam_cc_core_ahb_clk = {
1368 .halt_check = BRANCH_HALT_DELAY,
1370 .enable_reg = 0xc1a0,
1371 .enable_mask = BIT(0),
1372 .hw.init = &(struct clk_init_data){
1373 .name = "cam_cc_core_ahb_clk",
1374 .parent_hws = (const struct clk_hw*[]) {
1375 &cam_cc_slow_ahb_clk_src.clkr.hw,
1378 .flags = CLK_SET_RATE_PARENT,
1379 .ops = &clk_branch2_ops,
1384 static struct clk_branch cam_cc_cpas_ahb_clk = {
1386 .halt_check = BRANCH_HALT,
1388 .enable_reg = 0xc11c,
1389 .enable_mask = BIT(0),
1390 .hw.init = &(struct clk_init_data){
1391 .name = "cam_cc_cpas_ahb_clk",
1392 .parent_hws = (const struct clk_hw*[]) {
1393 &cam_cc_slow_ahb_clk_src.clkr.hw,
1396 .flags = CLK_SET_RATE_PARENT,
1397 .ops = &clk_branch2_ops,
1402 static struct clk_branch cam_cc_csi0phytimer_clk = {
1404 .halt_check = BRANCH_HALT,
1406 .enable_reg = 0xe0c4,
1407 .enable_mask = BIT(0),
1408 .hw.init = &(struct clk_init_data){
1409 .name = "cam_cc_csi0phytimer_clk",
1410 .parent_hws = (const struct clk_hw*[]) {
1411 &cam_cc_csi0phytimer_clk_src.clkr.hw,
1414 .flags = CLK_SET_RATE_PARENT,
1415 .ops = &clk_branch2_ops,
1420 static struct clk_branch cam_cc_csi1phytimer_clk = {
1422 .halt_check = BRANCH_HALT,
1424 .enable_reg = 0xe0e8,
1425 .enable_mask = BIT(0),
1426 .hw.init = &(struct clk_init_data){
1427 .name = "cam_cc_csi1phytimer_clk",
1428 .parent_hws = (const struct clk_hw*[]) {
1429 &cam_cc_csi1phytimer_clk_src.clkr.hw,
1432 .flags = CLK_SET_RATE_PARENT,
1433 .ops = &clk_branch2_ops,
1438 static struct clk_branch cam_cc_csi2phytimer_clk = {
1440 .halt_check = BRANCH_HALT,
1442 .enable_reg = 0xe10c,
1443 .enable_mask = BIT(0),
1444 .hw.init = &(struct clk_init_data){
1445 .name = "cam_cc_csi2phytimer_clk",
1446 .parent_hws = (const struct clk_hw*[]) {
1447 &cam_cc_csi2phytimer_clk_src.clkr.hw,
1450 .flags = CLK_SET_RATE_PARENT,
1451 .ops = &clk_branch2_ops,
1456 static struct clk_branch cam_cc_csi3phytimer_clk = {
1458 .halt_check = BRANCH_HALT,
1460 .enable_reg = 0xe134,
1461 .enable_mask = BIT(0),
1462 .hw.init = &(struct clk_init_data){
1463 .name = "cam_cc_csi3phytimer_clk",
1464 .parent_hws = (const struct clk_hw*[]) {
1465 &cam_cc_csi3phytimer_clk_src.clkr.hw,
1468 .flags = CLK_SET_RATE_PARENT,
1469 .ops = &clk_branch2_ops,
1474 static struct clk_branch cam_cc_csi4phytimer_clk = {
1476 .halt_check = BRANCH_HALT,
1478 .enable_reg = 0xe158,
1479 .enable_mask = BIT(0),
1480 .hw.init = &(struct clk_init_data){
1481 .name = "cam_cc_csi4phytimer_clk",
1482 .parent_hws = (const struct clk_hw*[]) {
1483 &cam_cc_csi4phytimer_clk_src.clkr.hw,
1486 .flags = CLK_SET_RATE_PARENT,
1487 .ops = &clk_branch2_ops,
1492 static struct clk_branch cam_cc_csiphy0_clk = {
1494 .halt_check = BRANCH_HALT,
1496 .enable_reg = 0xe0c8,
1497 .enable_mask = BIT(0),
1498 .hw.init = &(struct clk_init_data){
1499 .name = "cam_cc_csiphy0_clk",
1500 .parent_hws = (const struct clk_hw*[]) {
1501 &cam_cc_cphy_rx_clk_src.clkr.hw,
1504 .flags = CLK_SET_RATE_PARENT,
1505 .ops = &clk_branch2_ops,
1510 static struct clk_branch cam_cc_csiphy1_clk = {
1512 .halt_check = BRANCH_HALT,
1514 .enable_reg = 0xe0ec,
1515 .enable_mask = BIT(0),
1516 .hw.init = &(struct clk_init_data){
1517 .name = "cam_cc_csiphy1_clk",
1518 .parent_hws = (const struct clk_hw*[]) {
1519 &cam_cc_cphy_rx_clk_src.clkr.hw,
1522 .flags = CLK_SET_RATE_PARENT,
1523 .ops = &clk_branch2_ops,
1528 static struct clk_branch cam_cc_csiphy2_clk = {
1530 .halt_check = BRANCH_HALT,
1532 .enable_reg = 0xe110,
1533 .enable_mask = BIT(0),
1534 .hw.init = &(struct clk_init_data){
1535 .name = "cam_cc_csiphy2_clk",
1536 .parent_hws = (const struct clk_hw*[]) {
1537 &cam_cc_cphy_rx_clk_src.clkr.hw,
1540 .flags = CLK_SET_RATE_PARENT,
1541 .ops = &clk_branch2_ops,
1546 static struct clk_branch cam_cc_csiphy3_clk = {
1548 .halt_check = BRANCH_HALT,
1550 .enable_reg = 0xe138,
1551 .enable_mask = BIT(0),
1552 .hw.init = &(struct clk_init_data){
1553 .name = "cam_cc_csiphy3_clk",
1554 .parent_hws = (const struct clk_hw*[]) {
1555 &cam_cc_cphy_rx_clk_src.clkr.hw,
1558 .flags = CLK_SET_RATE_PARENT,
1559 .ops = &clk_branch2_ops,
1564 static struct clk_branch cam_cc_csiphy4_clk = {
1566 .halt_check = BRANCH_HALT,
1568 .enable_reg = 0xe15c,
1569 .enable_mask = BIT(0),
1570 .hw.init = &(struct clk_init_data){
1571 .name = "cam_cc_csiphy4_clk",
1572 .parent_hws = (const struct clk_hw*[]) {
1573 &cam_cc_cphy_rx_clk_src.clkr.hw,
1576 .flags = CLK_SET_RATE_PARENT,
1577 .ops = &clk_branch2_ops,
1582 static struct clk_branch cam_cc_gdsc_clk = {
1584 .halt_check = BRANCH_HALT,
1586 .enable_reg = 0xc1bc,
1587 .enable_mask = BIT(0),
1588 .hw.init = &(struct clk_init_data){
1589 .name = "cam_cc_gdsc_clk",
1590 .parent_hws = (const struct clk_hw*[]) {
1591 &cam_cc_xo_clk_src.clkr.hw,
1594 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1595 .ops = &clk_branch2_ops,
1600 static struct clk_branch cam_cc_icp_ahb_clk = {
1602 .halt_check = BRANCH_HALT,
1604 .enable_reg = 0xc0d8,
1605 .enable_mask = BIT(0),
1606 .hw.init = &(struct clk_init_data){
1607 .name = "cam_cc_icp_ahb_clk",
1608 .parent_hws = (const struct clk_hw*[]) {
1609 &cam_cc_slow_ahb_clk_src.clkr.hw,
1612 .flags = CLK_SET_RATE_PARENT,
1613 .ops = &clk_branch2_ops,
1618 static struct clk_branch cam_cc_icp_clk = {
1620 .halt_check = BRANCH_HALT,
1622 .enable_reg = 0xc0d0,
1623 .enable_mask = BIT(0),
1624 .hw.init = &(struct clk_init_data){
1625 .name = "cam_cc_icp_clk",
1626 .parent_hws = (const struct clk_hw*[]) {
1627 &cam_cc_icp_clk_src.clkr.hw,
1630 .flags = CLK_SET_RATE_PARENT,
1631 .ops = &clk_branch2_ops,
1636 static struct clk_branch cam_cc_ife_0_axi_clk = {
1638 .halt_check = BRANCH_HALT,
1640 .enable_reg = 0xa080,
1641 .enable_mask = BIT(0),
1642 .hw.init = &(struct clk_init_data){
1643 .name = "cam_cc_ife_0_axi_clk",
1644 .parent_hws = (const struct clk_hw*[]) {
1645 &cam_cc_camnoc_axi_clk_src.clkr.hw,
1648 .flags = CLK_SET_RATE_PARENT,
1649 .ops = &clk_branch2_ops,
1654 static struct clk_branch cam_cc_ife_0_clk = {
1656 .halt_check = BRANCH_HALT,
1658 .enable_reg = 0xa028,
1659 .enable_mask = BIT(0),
1660 .hw.init = &(struct clk_init_data){
1661 .name = "cam_cc_ife_0_clk",
1662 .parent_hws = (const struct clk_hw*[]) {
1663 &cam_cc_ife_0_clk_src.clkr.hw,
1666 .flags = CLK_SET_RATE_PARENT,
1667 .ops = &clk_branch2_ops,
1672 static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
1674 .halt_check = BRANCH_HALT,
1676 .enable_reg = 0xa07c,
1677 .enable_mask = BIT(0),
1678 .hw.init = &(struct clk_init_data){
1679 .name = "cam_cc_ife_0_cphy_rx_clk",
1680 .parent_hws = (const struct clk_hw*[]) {
1681 &cam_cc_cphy_rx_clk_src.clkr.hw,
1684 .flags = CLK_SET_RATE_PARENT,
1685 .ops = &clk_branch2_ops,
1690 static struct clk_branch cam_cc_ife_0_csid_clk = {
1692 .halt_check = BRANCH_HALT,
1694 .enable_reg = 0xa054,
1695 .enable_mask = BIT(0),
1696 .hw.init = &(struct clk_init_data){
1697 .name = "cam_cc_ife_0_csid_clk",
1698 .parent_hws = (const struct clk_hw*[]) {
1699 &cam_cc_ife_0_csid_clk_src.clkr.hw,
1702 .flags = CLK_SET_RATE_PARENT,
1703 .ops = &clk_branch2_ops,
1708 static struct clk_branch cam_cc_ife_0_dsp_clk = {
1710 .halt_check = BRANCH_HALT,
1712 .enable_reg = 0xa038,
1713 .enable_mask = BIT(0),
1714 .hw.init = &(struct clk_init_data){
1715 .name = "cam_cc_ife_0_dsp_clk",
1716 .parent_hws = (const struct clk_hw*[]) {
1717 &cam_cc_ife_0_clk_src.clkr.hw,
1720 .flags = CLK_SET_RATE_PARENT,
1721 .ops = &clk_branch2_ops,
1726 static struct clk_branch cam_cc_ife_1_axi_clk = {
1728 .halt_check = BRANCH_HALT,
1730 .enable_reg = 0xb068,
1731 .enable_mask = BIT(0),
1732 .hw.init = &(struct clk_init_data){
1733 .name = "cam_cc_ife_1_axi_clk",
1734 .parent_hws = (const struct clk_hw*[]) {
1735 &cam_cc_camnoc_axi_clk_src.clkr.hw,
1738 .flags = CLK_SET_RATE_PARENT,
1739 .ops = &clk_branch2_ops,
1744 static struct clk_branch cam_cc_ife_1_clk = {
1746 .halt_check = BRANCH_HALT,
1748 .enable_reg = 0xb028,
1749 .enable_mask = BIT(0),
1750 .hw.init = &(struct clk_init_data){
1751 .name = "cam_cc_ife_1_clk",
1752 .parent_hws = (const struct clk_hw*[]) {
1753 &cam_cc_ife_1_clk_src.clkr.hw,
1756 .flags = CLK_SET_RATE_PARENT,
1757 .ops = &clk_branch2_ops,
1762 static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
1764 .halt_check = BRANCH_HALT,
1766 .enable_reg = 0xb064,
1767 .enable_mask = BIT(0),
1768 .hw.init = &(struct clk_init_data){
1769 .name = "cam_cc_ife_1_cphy_rx_clk",
1770 .parent_hws = (const struct clk_hw*[]) {
1771 &cam_cc_cphy_rx_clk_src.clkr.hw,
1774 .flags = CLK_SET_RATE_PARENT,
1775 .ops = &clk_branch2_ops,
1780 static struct clk_branch cam_cc_ife_1_csid_clk = {
1782 .halt_check = BRANCH_HALT,
1784 .enable_reg = 0xb054,
1785 .enable_mask = BIT(0),
1786 .hw.init = &(struct clk_init_data){
1787 .name = "cam_cc_ife_1_csid_clk",
1788 .parent_hws = (const struct clk_hw*[]) {
1789 &cam_cc_ife_1_csid_clk_src.clkr.hw,
1792 .flags = CLK_SET_RATE_PARENT,
1793 .ops = &clk_branch2_ops,
1798 static struct clk_branch cam_cc_ife_1_dsp_clk = {
1800 .halt_check = BRANCH_HALT,
1802 .enable_reg = 0xb038,
1803 .enable_mask = BIT(0),
1804 .hw.init = &(struct clk_init_data){
1805 .name = "cam_cc_ife_1_dsp_clk",
1806 .parent_hws = (const struct clk_hw*[]) {
1807 &cam_cc_ife_1_clk_src.clkr.hw,
1810 .flags = CLK_SET_RATE_PARENT,
1811 .ops = &clk_branch2_ops,
1816 static struct clk_branch cam_cc_ife_2_axi_clk = {
1818 .halt_check = BRANCH_HALT,
1820 .enable_reg = 0xb0d4,
1821 .enable_mask = BIT(0),
1822 .hw.init = &(struct clk_init_data){
1823 .name = "cam_cc_ife_2_axi_clk",
1824 .parent_hws = (const struct clk_hw*[]) {
1825 &cam_cc_camnoc_axi_clk_src.clkr.hw,
1828 .flags = CLK_SET_RATE_PARENT,
1829 .ops = &clk_branch2_ops,
1834 static struct clk_branch cam_cc_ife_2_clk = {
1836 .halt_check = BRANCH_HALT,
1838 .enable_reg = 0xb094,
1839 .enable_mask = BIT(0),
1840 .hw.init = &(struct clk_init_data){
1841 .name = "cam_cc_ife_2_clk",
1842 .parent_hws = (const struct clk_hw*[]) {
1843 &cam_cc_ife_2_clk_src.clkr.hw,
1846 .flags = CLK_SET_RATE_PARENT,
1847 .ops = &clk_branch2_ops,
1852 static struct clk_branch cam_cc_ife_2_cphy_rx_clk = {
1854 .halt_check = BRANCH_HALT,
1856 .enable_reg = 0xb0d0,
1857 .enable_mask = BIT(0),
1858 .hw.init = &(struct clk_init_data){
1859 .name = "cam_cc_ife_2_cphy_rx_clk",
1860 .parent_hws = (const struct clk_hw*[]) {
1861 &cam_cc_cphy_rx_clk_src.clkr.hw,
1864 .flags = CLK_SET_RATE_PARENT,
1865 .ops = &clk_branch2_ops,
1870 static struct clk_branch cam_cc_ife_2_csid_clk = {
1872 .halt_check = BRANCH_HALT,
1874 .enable_reg = 0xb0c0,
1875 .enable_mask = BIT(0),
1876 .hw.init = &(struct clk_init_data){
1877 .name = "cam_cc_ife_2_csid_clk",
1878 .parent_hws = (const struct clk_hw*[]) {
1879 &cam_cc_ife_2_csid_clk_src.clkr.hw,
1882 .flags = CLK_SET_RATE_PARENT,
1883 .ops = &clk_branch2_ops,
1888 static struct clk_branch cam_cc_ife_2_dsp_clk = {
1890 .halt_check = BRANCH_HALT,
1892 .enable_reg = 0xb0a4,
1893 .enable_mask = BIT(0),
1894 .hw.init = &(struct clk_init_data){
1895 .name = "cam_cc_ife_2_dsp_clk",
1896 .parent_hws = (const struct clk_hw*[]) {
1897 &cam_cc_ife_2_clk_src.clkr.hw,
1900 .flags = CLK_SET_RATE_PARENT,
1901 .ops = &clk_branch2_ops,
1906 static struct clk_branch cam_cc_ife_lite_0_clk = {
1908 .halt_check = BRANCH_HALT,
1910 .enable_reg = 0xc01c,
1911 .enable_mask = BIT(0),
1912 .hw.init = &(struct clk_init_data){
1913 .name = "cam_cc_ife_lite_0_clk",
1914 .parent_hws = (const struct clk_hw*[]) {
1915 &cam_cc_ife_lite_0_clk_src.clkr.hw,
1918 .flags = CLK_SET_RATE_PARENT,
1919 .ops = &clk_branch2_ops,
1924 static struct clk_branch cam_cc_ife_lite_0_cphy_rx_clk = {
1926 .halt_check = BRANCH_HALT,
1928 .enable_reg = 0xc040,
1929 .enable_mask = BIT(0),
1930 .hw.init = &(struct clk_init_data){
1931 .name = "cam_cc_ife_lite_0_cphy_rx_clk",
1932 .parent_hws = (const struct clk_hw*[]) {
1933 &cam_cc_cphy_rx_clk_src.clkr.hw,
1936 .flags = CLK_SET_RATE_PARENT,
1937 .ops = &clk_branch2_ops,
1942 static struct clk_branch cam_cc_ife_lite_0_csid_clk = {
1944 .halt_check = BRANCH_HALT,
1946 .enable_reg = 0xc038,
1947 .enable_mask = BIT(0),
1948 .hw.init = &(struct clk_init_data){
1949 .name = "cam_cc_ife_lite_0_csid_clk",
1950 .parent_hws = (const struct clk_hw*[]) {
1951 &cam_cc_ife_lite_0_csid_clk_src.clkr.hw,
1954 .flags = CLK_SET_RATE_PARENT,
1955 .ops = &clk_branch2_ops,
1960 static struct clk_branch cam_cc_ife_lite_1_clk = {
1962 .halt_check = BRANCH_HALT,
1964 .enable_reg = 0xc060,
1965 .enable_mask = BIT(0),
1966 .hw.init = &(struct clk_init_data){
1967 .name = "cam_cc_ife_lite_1_clk",
1968 .parent_hws = (const struct clk_hw*[]) {
1969 &cam_cc_ife_lite_1_clk_src.clkr.hw,
1972 .flags = CLK_SET_RATE_PARENT,
1973 .ops = &clk_branch2_ops,
1978 static struct clk_branch cam_cc_ife_lite_1_cphy_rx_clk = {
1980 .halt_check = BRANCH_HALT,
1982 .enable_reg = 0xc084,
1983 .enable_mask = BIT(0),
1984 .hw.init = &(struct clk_init_data){
1985 .name = "cam_cc_ife_lite_1_cphy_rx_clk",
1986 .parent_hws = (const struct clk_hw*[]) {
1987 &cam_cc_cphy_rx_clk_src.clkr.hw,
1990 .flags = CLK_SET_RATE_PARENT,
1991 .ops = &clk_branch2_ops,
1996 static struct clk_branch cam_cc_ife_lite_1_csid_clk = {
1998 .halt_check = BRANCH_HALT,
2000 .enable_reg = 0xc07c,
2001 .enable_mask = BIT(0),
2002 .hw.init = &(struct clk_init_data){
2003 .name = "cam_cc_ife_lite_1_csid_clk",
2004 .parent_hws = (const struct clk_hw*[]) {
2005 &cam_cc_ife_lite_1_csid_clk_src.clkr.hw,
2008 .flags = CLK_SET_RATE_PARENT,
2009 .ops = &clk_branch2_ops,
2014 static struct clk_branch cam_cc_ipe_0_ahb_clk = {
2016 .halt_check = BRANCH_HALT,
2018 .enable_reg = 0x8040,
2019 .enable_mask = BIT(0),
2020 .hw.init = &(struct clk_init_data){
2021 .name = "cam_cc_ipe_0_ahb_clk",
2022 .parent_hws = (const struct clk_hw*[]) {
2023 &cam_cc_slow_ahb_clk_src.clkr.hw,
2026 .flags = CLK_SET_RATE_PARENT,
2027 .ops = &clk_branch2_ops,
2032 static struct clk_branch cam_cc_ipe_0_areg_clk = {
2034 .halt_check = BRANCH_HALT,
2036 .enable_reg = 0x803c,
2037 .enable_mask = BIT(0),
2038 .hw.init = &(struct clk_init_data){
2039 .name = "cam_cc_ipe_0_areg_clk",
2040 .parent_hws = (const struct clk_hw*[]) {
2041 &cam_cc_fast_ahb_clk_src.clkr.hw,
2044 .flags = CLK_SET_RATE_PARENT,
2045 .ops = &clk_branch2_ops,
2050 static struct clk_branch cam_cc_ipe_0_axi_clk = {
2052 .halt_check = BRANCH_HALT,
2054 .enable_reg = 0x8038,
2055 .enable_mask = BIT(0),
2056 .hw.init = &(struct clk_init_data){
2057 .name = "cam_cc_ipe_0_axi_clk",
2058 .parent_hws = (const struct clk_hw*[]) {
2059 &cam_cc_camnoc_axi_clk_src.clkr.hw,
2062 .flags = CLK_SET_RATE_PARENT,
2063 .ops = &clk_branch2_ops,
2068 static struct clk_branch cam_cc_ipe_0_clk = {
2070 .halt_check = BRANCH_HALT,
2072 .enable_reg = 0x8028,
2073 .enable_mask = BIT(0),
2074 .hw.init = &(struct clk_init_data){
2075 .name = "cam_cc_ipe_0_clk",
2076 .parent_hws = (const struct clk_hw*[]) {
2077 &cam_cc_ipe_0_clk_src.clkr.hw,
2080 .flags = CLK_SET_RATE_PARENT,
2081 .ops = &clk_branch2_ops,
2086 static struct clk_branch cam_cc_jpeg_clk = {
2088 .halt_check = BRANCH_HALT,
2090 .enable_reg = 0xc0a4,
2091 .enable_mask = BIT(0),
2092 .hw.init = &(struct clk_init_data){
2093 .name = "cam_cc_jpeg_clk",
2094 .parent_hws = (const struct clk_hw*[]) {
2095 &cam_cc_jpeg_clk_src.clkr.hw,
2098 .flags = CLK_SET_RATE_PARENT,
2099 .ops = &clk_branch2_ops,
2104 static struct clk_branch cam_cc_lrme_clk = {
2106 .halt_check = BRANCH_HALT,
2108 .enable_reg = 0xc168,
2109 .enable_mask = BIT(0),
2110 .hw.init = &(struct clk_init_data){
2111 .name = "cam_cc_lrme_clk",
2112 .parent_hws = (const struct clk_hw*[]) {
2113 &cam_cc_lrme_clk_src.clkr.hw,
2116 .flags = CLK_SET_RATE_PARENT,
2117 .ops = &clk_branch2_ops,
2122 static struct clk_branch cam_cc_mclk0_clk = {
2124 .halt_check = BRANCH_HALT,
2126 .enable_reg = 0xe018,
2127 .enable_mask = BIT(0),
2128 .hw.init = &(struct clk_init_data){
2129 .name = "cam_cc_mclk0_clk",
2130 .parent_hws = (const struct clk_hw*[]) {
2131 &cam_cc_mclk0_clk_src.clkr.hw,
2134 .flags = CLK_SET_RATE_PARENT,
2135 .ops = &clk_branch2_ops,
2140 static struct clk_branch cam_cc_mclk1_clk = {
2142 .halt_check = BRANCH_HALT,
2144 .enable_reg = 0xe034,
2145 .enable_mask = BIT(0),
2146 .hw.init = &(struct clk_init_data){
2147 .name = "cam_cc_mclk1_clk",
2148 .parent_hws = (const struct clk_hw*[]) {
2149 &cam_cc_mclk1_clk_src.clkr.hw,
2152 .flags = CLK_SET_RATE_PARENT,
2153 .ops = &clk_branch2_ops,
2158 static struct clk_branch cam_cc_mclk2_clk = {
2160 .halt_check = BRANCH_HALT,
2162 .enable_reg = 0xe050,
2163 .enable_mask = BIT(0),
2164 .hw.init = &(struct clk_init_data){
2165 .name = "cam_cc_mclk2_clk",
2166 .parent_hws = (const struct clk_hw*[]) {
2167 &cam_cc_mclk2_clk_src.clkr.hw,
2170 .flags = CLK_SET_RATE_PARENT,
2171 .ops = &clk_branch2_ops,
2176 static struct clk_branch cam_cc_mclk3_clk = {
2178 .halt_check = BRANCH_HALT,
2180 .enable_reg = 0xe06c,
2181 .enable_mask = BIT(0),
2182 .hw.init = &(struct clk_init_data){
2183 .name = "cam_cc_mclk3_clk",
2184 .parent_hws = (const struct clk_hw*[]) {
2185 &cam_cc_mclk3_clk_src.clkr.hw,
2188 .flags = CLK_SET_RATE_PARENT,
2189 .ops = &clk_branch2_ops,
2194 static struct clk_branch cam_cc_mclk4_clk = {
2196 .halt_check = BRANCH_HALT,
2198 .enable_reg = 0xe088,
2199 .enable_mask = BIT(0),
2200 .hw.init = &(struct clk_init_data){
2201 .name = "cam_cc_mclk4_clk",
2202 .parent_hws = (const struct clk_hw*[]) {
2203 &cam_cc_mclk4_clk_src.clkr.hw,
2206 .flags = CLK_SET_RATE_PARENT,
2207 .ops = &clk_branch2_ops,
2212 static struct clk_branch cam_cc_mclk5_clk = {
2214 .halt_check = BRANCH_HALT,
2216 .enable_reg = 0xe0a4,
2217 .enable_mask = BIT(0),
2218 .hw.init = &(struct clk_init_data){
2219 .name = "cam_cc_mclk5_clk",
2220 .parent_hws = (const struct clk_hw*[]) {
2221 &cam_cc_mclk5_clk_src.clkr.hw,
2224 .flags = CLK_SET_RATE_PARENT,
2225 .ops = &clk_branch2_ops,
2230 static struct clk_branch cam_cc_sleep_clk = {
2232 .halt_check = BRANCH_HALT,
2234 .enable_reg = 0xc1d8,
2235 .enable_mask = BIT(0),
2236 .hw.init = &(struct clk_init_data){
2237 .name = "cam_cc_sleep_clk",
2238 .parent_hws = (const struct clk_hw*[]) {
2239 &cam_cc_sleep_clk_src.clkr.hw,
2242 .flags = CLK_SET_RATE_PARENT,
2243 .ops = &clk_branch2_ops,
2248 static struct gdsc cam_cc_titan_top_gdsc = {
2251 .name = "cam_cc_titan_top_gdsc",
2253 .pwrsts = PWRSTS_OFF_ON,
2254 .flags = RETAIN_FF_ENABLE,
2257 static struct gdsc cam_cc_bps_gdsc = {
2260 .name = "cam_cc_bps_gdsc",
2262 .pwrsts = PWRSTS_OFF_ON,
2263 .flags = HW_CTRL | RETAIN_FF_ENABLE,
2266 static struct gdsc cam_cc_ife_0_gdsc = {
2269 .name = "cam_cc_ife_0_gdsc",
2271 .pwrsts = PWRSTS_OFF_ON,
2272 .flags = RETAIN_FF_ENABLE,
2275 static struct gdsc cam_cc_ife_1_gdsc = {
2278 .name = "cam_cc_ife_1_gdsc",
2280 .pwrsts = PWRSTS_OFF_ON,
2281 .flags = RETAIN_FF_ENABLE,
2284 static struct gdsc cam_cc_ife_2_gdsc = {
2287 .name = "cam_cc_ife_2_gdsc",
2289 .pwrsts = PWRSTS_OFF_ON,
2290 .flags = RETAIN_FF_ENABLE,
2293 static struct gdsc cam_cc_ipe_0_gdsc = {
2296 .name = "cam_cc_ipe_0_gdsc",
2298 .pwrsts = PWRSTS_OFF_ON,
2299 .flags = HW_CTRL | RETAIN_FF_ENABLE,
2302 static struct clk_regmap *cam_cc_sc7280_clocks[] = {
2303 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
2304 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr,
2305 [CAM_CC_BPS_AXI_CLK] = &cam_cc_bps_axi_clk.clkr,
2306 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
2307 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
2308 [CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
2309 [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
2310 [CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
2311 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
2312 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
2313 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
2314 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
2315 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
2316 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
2317 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
2318 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
2319 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
2320 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
2321 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
2322 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
2323 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
2324 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
2325 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
2326 [CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
2327 [CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
2328 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
2329 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
2330 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
2331 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
2332 [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
2333 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
2334 [CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr,
2335 [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
2336 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
2337 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
2338 [CAM_CC_IFE_0_AXI_CLK] = &cam_cc_ife_0_axi_clk.clkr,
2339 [CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
2340 [CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
2341 [CAM_CC_IFE_0_CPHY_RX_CLK] = &cam_cc_ife_0_cphy_rx_clk.clkr,
2342 [CAM_CC_IFE_0_CSID_CLK] = &cam_cc_ife_0_csid_clk.clkr,
2343 [CAM_CC_IFE_0_CSID_CLK_SRC] = &cam_cc_ife_0_csid_clk_src.clkr,
2344 [CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
2345 [CAM_CC_IFE_1_AXI_CLK] = &cam_cc_ife_1_axi_clk.clkr,
2346 [CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
2347 [CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
2348 [CAM_CC_IFE_1_CPHY_RX_CLK] = &cam_cc_ife_1_cphy_rx_clk.clkr,
2349 [CAM_CC_IFE_1_CSID_CLK] = &cam_cc_ife_1_csid_clk.clkr,
2350 [CAM_CC_IFE_1_CSID_CLK_SRC] = &cam_cc_ife_1_csid_clk_src.clkr,
2351 [CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
2352 [CAM_CC_IFE_2_AXI_CLK] = &cam_cc_ife_2_axi_clk.clkr,
2353 [CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr,
2354 [CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr,
2355 [CAM_CC_IFE_2_CPHY_RX_CLK] = &cam_cc_ife_2_cphy_rx_clk.clkr,
2356 [CAM_CC_IFE_2_CSID_CLK] = &cam_cc_ife_2_csid_clk.clkr,
2357 [CAM_CC_IFE_2_CSID_CLK_SRC] = &cam_cc_ife_2_csid_clk_src.clkr,
2358 [CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr,
2359 [CAM_CC_IFE_LITE_0_CLK] = &cam_cc_ife_lite_0_clk.clkr,
2360 [CAM_CC_IFE_LITE_0_CLK_SRC] = &cam_cc_ife_lite_0_clk_src.clkr,
2361 [CAM_CC_IFE_LITE_0_CPHY_RX_CLK] = &cam_cc_ife_lite_0_cphy_rx_clk.clkr,
2362 [CAM_CC_IFE_LITE_0_CSID_CLK] = &cam_cc_ife_lite_0_csid_clk.clkr,
2363 [CAM_CC_IFE_LITE_0_CSID_CLK_SRC] = &cam_cc_ife_lite_0_csid_clk_src.clkr,
2364 [CAM_CC_IFE_LITE_1_CLK] = &cam_cc_ife_lite_1_clk.clkr,
2365 [CAM_CC_IFE_LITE_1_CLK_SRC] = &cam_cc_ife_lite_1_clk_src.clkr,
2366 [CAM_CC_IFE_LITE_1_CPHY_RX_CLK] = &cam_cc_ife_lite_1_cphy_rx_clk.clkr,
2367 [CAM_CC_IFE_LITE_1_CSID_CLK] = &cam_cc_ife_lite_1_csid_clk.clkr,
2368 [CAM_CC_IFE_LITE_1_CSID_CLK_SRC] = &cam_cc_ife_lite_1_csid_clk_src.clkr,
2369 [CAM_CC_IPE_0_AHB_CLK] = &cam_cc_ipe_0_ahb_clk.clkr,
2370 [CAM_CC_IPE_0_AREG_CLK] = &cam_cc_ipe_0_areg_clk.clkr,
2371 [CAM_CC_IPE_0_AXI_CLK] = &cam_cc_ipe_0_axi_clk.clkr,
2372 [CAM_CC_IPE_0_CLK] = &cam_cc_ipe_0_clk.clkr,
2373 [CAM_CC_IPE_0_CLK_SRC] = &cam_cc_ipe_0_clk_src.clkr,
2374 [CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
2375 [CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
2376 [CAM_CC_LRME_CLK] = &cam_cc_lrme_clk.clkr,
2377 [CAM_CC_LRME_CLK_SRC] = &cam_cc_lrme_clk_src.clkr,
2378 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
2379 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
2380 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
2381 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
2382 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
2383 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
2384 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
2385 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
2386 [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
2387 [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
2388 [CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
2389 [CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
2390 [CAM_CC_PLL0] = &cam_cc_pll0.clkr,
2391 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
2392 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
2393 [CAM_CC_PLL1] = &cam_cc_pll1.clkr,
2394 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
2395 [CAM_CC_PLL2] = &cam_cc_pll2.clkr,
2396 [CAM_CC_PLL2_OUT_AUX] = &cam_cc_pll2_out_aux.clkr,
2397 [CAM_CC_PLL2_OUT_AUX2] = &cam_cc_pll2_out_aux2.clkr,
2398 [CAM_CC_PLL3] = &cam_cc_pll3.clkr,
2399 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
2400 [CAM_CC_PLL4] = &cam_cc_pll4.clkr,
2401 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
2402 [CAM_CC_PLL5] = &cam_cc_pll5.clkr,
2403 [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr,
2404 [CAM_CC_PLL6] = &cam_cc_pll6.clkr,
2405 [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr,
2406 [CAM_CC_PLL6_OUT_ODD] = &cam_cc_pll6_out_odd.clkr,
2407 [CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr,
2408 [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
2409 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
2410 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
2413 static struct gdsc *cam_cc_sc7280_gdscs[] = {
2414 [CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc,
2415 [CAM_CC_BPS_GDSC] = &cam_cc_bps_gdsc,
2416 [CAM_CC_IFE_0_GDSC] = &cam_cc_ife_0_gdsc,
2417 [CAM_CC_IFE_1_GDSC] = &cam_cc_ife_1_gdsc,
2418 [CAM_CC_IFE_2_GDSC] = &cam_cc_ife_2_gdsc,
2419 [CAM_CC_IPE_0_GDSC] = &cam_cc_ipe_0_gdsc,
2422 static const struct regmap_config cam_cc_sc7280_regmap_config = {
2426 .max_register = 0xf00c,
2430 static const struct qcom_cc_desc cam_cc_sc7280_desc = {
2431 .config = &cam_cc_sc7280_regmap_config,
2432 .clks = cam_cc_sc7280_clocks,
2433 .num_clks = ARRAY_SIZE(cam_cc_sc7280_clocks),
2434 .gdscs = cam_cc_sc7280_gdscs,
2435 .num_gdscs = ARRAY_SIZE(cam_cc_sc7280_gdscs),
2438 static const struct of_device_id cam_cc_sc7280_match_table[] = {
2439 { .compatible = "qcom,sc7280-camcc" },
2442 MODULE_DEVICE_TABLE(of, cam_cc_sc7280_match_table);
2444 static int cam_cc_sc7280_probe(struct platform_device *pdev)
2446 struct regmap *regmap;
2448 regmap = qcom_cc_map(pdev, &cam_cc_sc7280_desc);
2450 return PTR_ERR(regmap);
2452 clk_lucid_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
2453 clk_lucid_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
2454 clk_zonda_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
2455 clk_lucid_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
2456 clk_lucid_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
2457 clk_lucid_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
2458 clk_lucid_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
2460 return qcom_cc_really_probe(pdev, &cam_cc_sc7280_desc, regmap);
2463 static struct platform_driver cam_cc_sc7280_driver = {
2464 .probe = cam_cc_sc7280_probe,
2466 .name = "cam_cc-sc7280",
2467 .of_match_table = cam_cc_sc7280_match_table,
2471 static int __init cam_cc_sc7280_init(void)
2473 return platform_driver_register(&cam_cc_sc7280_driver);
2475 subsys_initcall(cam_cc_sc7280_init);
2477 static void __exit cam_cc_sc7280_exit(void)
2479 platform_driver_unregister(&cam_cc_sc7280_driver);
2481 module_exit(cam_cc_sc7280_exit);
2483 MODULE_DESCRIPTION("QTI CAM_CC SC7280 Driver");
2484 MODULE_LICENSE("GPL v2");