1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 #ifndef _ASM_POWERPC_CACHEFLUSH_H
5 #define _ASM_POWERPC_CACHEFLUSH_H
8 #include <asm/cputable.h>
9 #include <asm/cpu_has_feature.h>
12 * This flag is used to indicate that the page pointed to by a pte is clean
13 * and does not require cleaning before returning it to the user.
15 #define PG_dcache_clean PG_arch_1
17 #ifdef CONFIG_PPC_BOOK3S_64
19 * Book3s has no ptesync after setting a pte, so without this ptesync it's
20 * possible for a kernel virtual mapping access to return a spurious fault
21 * if it's accessed right after the pte is set. The page fault handler does
22 * not expect this type of fault. flush_cache_vmap is not exactly the right
23 * place to put this, but it seems to work well enough.
25 static inline void flush_cache_vmap(unsigned long start, unsigned long end)
27 asm volatile("ptesync" ::: "memory");
29 #define flush_cache_vmap flush_cache_vmap
30 #endif /* CONFIG_PPC_BOOK3S_64 */
32 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
34 * This is called when a page has been modified by the kernel.
35 * It just marks the page as not i-cache clean. We do the i-cache
36 * flush later when the page is given to a user process, if necessary.
38 static inline void flush_dcache_folio(struct folio *folio)
40 if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
42 /* avoid an atomic op if possible */
43 if (test_bit(PG_dcache_clean, &folio->flags))
44 clear_bit(PG_dcache_clean, &folio->flags);
46 #define flush_dcache_folio flush_dcache_folio
48 static inline void flush_dcache_page(struct page *page)
50 flush_dcache_folio(page_folio(page));
53 void flush_icache_range(unsigned long start, unsigned long stop);
54 #define flush_icache_range flush_icache_range
56 void flush_icache_user_page(struct vm_area_struct *vma, struct page *page,
57 unsigned long addr, int len);
58 #define flush_icache_user_page flush_icache_user_page
60 void flush_dcache_icache_folio(struct folio *folio);
63 * flush_dcache_range(): Write any modified data cache blocks out to memory and
64 * invalidate them. Does not invalidate the corresponding instruction cache
67 * @start: the start address
68 * @stop: the stop address (exclusive)
70 static inline void flush_dcache_range(unsigned long start, unsigned long stop)
72 unsigned long shift = l1_dcache_shift();
73 unsigned long bytes = l1_dcache_bytes();
74 void *addr = (void *)(start & ~(bytes - 1));
75 unsigned long size = stop - (unsigned long)addr + (bytes - 1);
78 if (IS_ENABLED(CONFIG_PPC64))
81 for (i = 0; i < size >> shift; i++, addr += bytes)
88 * Write any modified data cache blocks out to memory.
89 * Does not invalidate the corresponding cache lines (especially for
90 * any corresponding instruction cache).
92 static inline void clean_dcache_range(unsigned long start, unsigned long stop)
94 unsigned long shift = l1_dcache_shift();
95 unsigned long bytes = l1_dcache_bytes();
96 void *addr = (void *)(start & ~(bytes - 1));
97 unsigned long size = stop - (unsigned long)addr + (bytes - 1);
100 for (i = 0; i < size >> shift; i++, addr += bytes)
106 * Like above, but invalidate the D-cache. This is used by the 8xx
107 * to invalidate the cache so the PPC core doesn't get stale data
108 * from the CPM (no cache snooping here :-).
110 static inline void invalidate_dcache_range(unsigned long start,
113 unsigned long shift = l1_dcache_shift();
114 unsigned long bytes = l1_dcache_bytes();
115 void *addr = (void *)(start & ~(bytes - 1));
116 unsigned long size = stop - (unsigned long)addr + (bytes - 1);
119 for (i = 0; i < size >> shift; i++, addr += bytes)
125 static inline void flush_instruction_cache(void)
127 iccci((void *)KERNELBASE);
131 void flush_instruction_cache(void);
134 #include <asm-generic/cacheflush.h>
136 #endif /* _ASM_POWERPC_CACHEFLUSH_H */