2 * arch/xtensa/mm/cache.c
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2001-2006 Tensilica Inc.
10 * Chris Zankel <chris@zankel.net>
16 #include <linux/init.h>
17 #include <linux/signal.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/string.h>
22 #include <linux/types.h>
23 #include <linux/ptrace.h>
24 #include <linux/bootmem.h>
25 #include <linux/swap.h>
26 #include <linux/pagemap.h>
28 #include <asm/bootparam.h>
29 #include <asm/mmu_context.h>
31 #include <asm/tlbflush.h>
33 #include <asm/pgalloc.h>
34 #include <asm/pgtable.h>
38 * The kernel provides one architecture bit PG_arch_1 in the page flags that
39 * can be used for cache coherency.
43 * The Xtensa architecture doesn't keep the instruction cache coherent with
44 * the data cache. We use the architecture bit to indicate if the caches
45 * are coherent. The kernel clears this bit whenever a page is added to the
46 * page cache. At that time, the caches might not be in sync. We, therefore,
47 * define this flag as 'clean' if set.
51 * With cache aliasing, we have to always flush the cache when pages are
52 * unmapped (see tlb_start_vma(). So, we use this flag to indicate a dirty
59 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
60 static inline void kmap_invalidate_coherent(struct page *page,
63 if (!DCACHE_ALIAS_EQ(page_to_phys(page), vaddr)) {
66 if (!PageHighMem(page)) {
67 kvaddr = (unsigned long)page_to_virt(page);
69 __invalidate_dcache_page(kvaddr);
71 kvaddr = TLBTEMP_BASE_1 +
72 (page_to_phys(page) & DCACHE_ALIAS_MASK);
75 __invalidate_dcache_page_alias(kvaddr,
82 static inline void *coherent_kvaddr(struct page *page, unsigned long base,
83 unsigned long vaddr, unsigned long *paddr)
85 if (PageHighMem(page) || !DCACHE_ALIAS_EQ(page_to_phys(page), vaddr)) {
86 *paddr = page_to_phys(page);
87 return (void *)(base + (vaddr & DCACHE_ALIAS_MASK));
90 return page_to_virt(page);
94 void clear_user_highpage(struct page *page, unsigned long vaddr)
97 void *kvaddr = coherent_kvaddr(page, TLBTEMP_BASE_1, vaddr, &paddr);
100 kmap_invalidate_coherent(page, vaddr);
101 set_bit(PG_arch_1, &page->flags);
102 clear_page_alias(kvaddr, paddr);
105 EXPORT_SYMBOL(clear_user_highpage);
107 void copy_user_highpage(struct page *dst, struct page *src,
108 unsigned long vaddr, struct vm_area_struct *vma)
110 unsigned long dst_paddr, src_paddr;
111 void *dst_vaddr = coherent_kvaddr(dst, TLBTEMP_BASE_1, vaddr,
113 void *src_vaddr = coherent_kvaddr(src, TLBTEMP_BASE_2, vaddr,
117 kmap_invalidate_coherent(dst, vaddr);
118 set_bit(PG_arch_1, &dst->flags);
119 copy_page_alias(dst_vaddr, src_vaddr, dst_paddr, src_paddr);
122 EXPORT_SYMBOL(copy_user_highpage);
125 * Any time the kernel writes to a user page cache page, or it is about to
126 * read from a page cache page this routine is called.
130 void flush_dcache_page(struct page *page)
132 struct address_space *mapping = page_mapping_file(page);
135 * If we have a mapping but the page is not mapped to user-space
136 * yet, we simply mark this page dirty and defer flushing the
137 * caches until update_mmu().
140 if (mapping && !mapping_mapped(mapping)) {
141 if (!test_bit(PG_arch_1, &page->flags))
142 set_bit(PG_arch_1, &page->flags);
147 unsigned long phys = page_to_phys(page);
148 unsigned long temp = page->index << PAGE_SHIFT;
149 unsigned long alias = !(DCACHE_ALIAS_EQ(temp, phys));
153 * Flush the page in kernel space and user space.
154 * Note that we can omit that step if aliasing is not
155 * an issue, but we do have to synchronize I$ and D$
156 * if we have a mapping.
159 if (!alias && !mapping)
163 virt = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK);
164 __flush_invalidate_dcache_page_alias(virt, phys);
166 virt = TLBTEMP_BASE_1 + (temp & DCACHE_ALIAS_MASK);
169 __flush_invalidate_dcache_page_alias(virt, phys);
172 __invalidate_icache_page_alias(virt, phys);
176 /* There shouldn't be an entry in the cache for this page anymore. */
178 EXPORT_SYMBOL(flush_dcache_page);
181 * For now, flush the whole cache. FIXME??
184 void local_flush_cache_range(struct vm_area_struct *vma,
185 unsigned long start, unsigned long end)
187 __flush_invalidate_dcache_all();
188 __invalidate_icache_all();
190 EXPORT_SYMBOL(local_flush_cache_range);
193 * Remove any entry in the cache for this page.
195 * Note that this function is only called for user pages, so use the
196 * alias versions of the cache flush functions.
199 void local_flush_cache_page(struct vm_area_struct *vma, unsigned long address,
202 /* Note that we have to use the 'alias' address to avoid multi-hit */
204 unsigned long phys = page_to_phys(pfn_to_page(pfn));
205 unsigned long virt = TLBTEMP_BASE_1 + (address & DCACHE_ALIAS_MASK);
208 __flush_invalidate_dcache_page_alias(virt, phys);
209 __invalidate_icache_page_alias(virt, phys);
212 EXPORT_SYMBOL(local_flush_cache_page);
214 #endif /* DCACHE_WAY_SIZE > PAGE_SIZE */
217 update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *ptep)
219 unsigned long pfn = pte_pfn(*ptep);
225 page = pfn_to_page(pfn);
227 /* Invalidate old entry in TLBs */
229 flush_tlb_page(vma, addr);
231 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
233 if (!PageReserved(page) && test_bit(PG_arch_1, &page->flags)) {
234 unsigned long phys = page_to_phys(page);
238 tmp = TLBTEMP_BASE_1 + (phys & DCACHE_ALIAS_MASK);
239 __flush_invalidate_dcache_page_alias(tmp, phys);
240 tmp = TLBTEMP_BASE_1 + (addr & DCACHE_ALIAS_MASK);
241 __flush_invalidate_dcache_page_alias(tmp, phys);
242 __invalidate_icache_page_alias(tmp, phys);
245 clear_bit(PG_arch_1, &page->flags);
248 if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags)
249 && (vma->vm_flags & VM_EXEC) != 0) {
250 unsigned long paddr = (unsigned long)kmap_atomic(page);
251 __flush_dcache_page(paddr);
252 __invalidate_icache_page(paddr);
253 set_bit(PG_arch_1, &page->flags);
254 kunmap_atomic((void *)paddr);
260 * access_process_vm() has called get_user_pages(), which has done a
261 * flush_dcache_page() on the page.
264 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
266 void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
267 unsigned long vaddr, void *dst, const void *src,
270 unsigned long phys = page_to_phys(page);
271 unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys));
273 /* Flush and invalidate user page if aliased. */
276 unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
278 __flush_invalidate_dcache_page_alias(t, phys);
284 memcpy(dst, src, len);
287 * Flush and invalidate kernel page if aliased and synchronize
288 * data and instruction caches for executable pages.
292 unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
295 __flush_invalidate_dcache_range((unsigned long) dst, len);
296 if ((vma->vm_flags & VM_EXEC) != 0)
297 __invalidate_icache_page_alias(t, phys);
300 } else if ((vma->vm_flags & VM_EXEC) != 0) {
301 __flush_dcache_range((unsigned long)dst,len);
302 __invalidate_icache_range((unsigned long) dst, len);
306 extern void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
307 unsigned long vaddr, void *dst, const void *src,
310 unsigned long phys = page_to_phys(page);
311 unsigned long alias = !(DCACHE_ALIAS_EQ(vaddr, phys));
314 * Flush user page if aliased.
315 * (Note: a simply flush would be sufficient)
319 unsigned long t = TLBTEMP_BASE_1 + (vaddr & DCACHE_ALIAS_MASK);
321 __flush_invalidate_dcache_page_alias(t, phys);
325 memcpy(dst, src, len);