1 // SPDX-License-Identifier: GPL-2.0
3 * Just-In-Time compiler for eBPF filters on IA32 (32bit x86)
5 * Author: Wang YanQing (udknight@gmail.com)
6 * The code based on code and ideas from:
7 * Eric Dumazet (eric.dumazet@gmail.com)
9 * Shubham Bansal <illusionist.neo@gmail.com>
12 #include <linux/netdevice.h>
13 #include <linux/filter.h>
14 #include <linux/if_vlan.h>
15 #include <asm/cacheflush.h>
16 #include <asm/set_memory.h>
17 #include <asm/nospec-branch.h>
18 #include <linux/bpf.h>
21 * eBPF prog stack layout:
24 * original ESP => +-----+
25 * | | callee saved registers
27 * | ... | eBPF JIT scratch space
28 * BPF_FP,IA32_EBP => +-----+
29 * | ... | eBPF prog stack
31 * |RSVD | JIT scratchpad
32 * current ESP => +-----+
34 * | ... | Function call stack
39 * The callee saved registers:
42 * original ESP => +------------------+ \
44 * current EBP => +------------------+ } callee saved registers
46 * +------------------+ /
50 static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len)
63 #define EMIT(bytes, len) \
64 do { prog = emit_code(prog, bytes, len); cnt += len; } while (0)
66 #define EMIT1(b1) EMIT(b1, 1)
67 #define EMIT2(b1, b2) EMIT((b1) + ((b2) << 8), 2)
68 #define EMIT3(b1, b2, b3) EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
69 #define EMIT4(b1, b2, b3, b4) \
70 EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
72 #define EMIT1_off32(b1, off) \
73 do { EMIT1(b1); EMIT(off, 4); } while (0)
74 #define EMIT2_off32(b1, b2, off) \
75 do { EMIT2(b1, b2); EMIT(off, 4); } while (0)
76 #define EMIT3_off32(b1, b2, b3, off) \
77 do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
78 #define EMIT4_off32(b1, b2, b3, b4, off) \
79 do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
81 #define jmp_label(label, jmp_insn_len) (label - cnt - jmp_insn_len)
83 static bool is_imm8(int value)
85 return value <= 127 && value >= -128;
88 static bool is_simm32(s64 value)
90 return value == (s64) (s32) value;
93 #define STACK_OFFSET(k) (k)
94 #define TCALL_CNT (MAX_BPF_JIT_REG + 0) /* Tail Call Count */
96 #define IA32_EAX (0x0)
97 #define IA32_EBX (0x3)
98 #define IA32_ECX (0x1)
99 #define IA32_EDX (0x2)
100 #define IA32_ESI (0x6)
101 #define IA32_EDI (0x7)
102 #define IA32_EBP (0x5)
103 #define IA32_ESP (0x4)
106 * List of x86 cond jumps opcodes (. + s8)
107 * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32)
110 #define IA32_JAE 0x73
112 #define IA32_JNE 0x75
113 #define IA32_JBE 0x76
116 #define IA32_JGE 0x7D
117 #define IA32_JLE 0x7E
120 #define COND_JMP_OPCODE_INVALID (0xFF)
123 * Map eBPF registers to IA32 32bit registers or stack scratch space.
125 * 1. All the registers, R0-R10, are mapped to scratch space on stack.
126 * 2. We need two 64 bit temp registers to do complex operations on eBPF
128 * 3. For performance reason, the BPF_REG_AX for blinding constant, is
129 * mapped to real hardware register pair, IA32_ESI and IA32_EDI.
131 * As the eBPF registers are all 64 bit registers and IA32 has only 32 bit
132 * registers, we have to map each eBPF registers with two IA32 32 bit regs
133 * or scratch memory space and we have to build eBPF 64 bit register from those.
135 * We use IA32_EAX, IA32_EDX, IA32_ECX, IA32_EBX as temporary registers.
137 static const u8 bpf2ia32[][2] = {
138 /* Return value from in-kernel function, and exit value from eBPF */
139 [BPF_REG_0] = {STACK_OFFSET(0), STACK_OFFSET(4)},
141 /* The arguments from eBPF program to in-kernel function */
142 /* Stored on stack scratch space */
143 [BPF_REG_1] = {STACK_OFFSET(8), STACK_OFFSET(12)},
144 [BPF_REG_2] = {STACK_OFFSET(16), STACK_OFFSET(20)},
145 [BPF_REG_3] = {STACK_OFFSET(24), STACK_OFFSET(28)},
146 [BPF_REG_4] = {STACK_OFFSET(32), STACK_OFFSET(36)},
147 [BPF_REG_5] = {STACK_OFFSET(40), STACK_OFFSET(44)},
149 /* Callee saved registers that in-kernel function will preserve */
150 /* Stored on stack scratch space */
151 [BPF_REG_6] = {STACK_OFFSET(48), STACK_OFFSET(52)},
152 [BPF_REG_7] = {STACK_OFFSET(56), STACK_OFFSET(60)},
153 [BPF_REG_8] = {STACK_OFFSET(64), STACK_OFFSET(68)},
154 [BPF_REG_9] = {STACK_OFFSET(72), STACK_OFFSET(76)},
156 /* Read only Frame Pointer to access Stack */
157 [BPF_REG_FP] = {STACK_OFFSET(80), STACK_OFFSET(84)},
159 /* Temporary register for blinding constants. */
160 [BPF_REG_AX] = {IA32_ESI, IA32_EDI},
162 /* Tail call count. Stored on stack scratch space. */
163 [TCALL_CNT] = {STACK_OFFSET(88), STACK_OFFSET(92)},
166 #define dst_lo dst[0]
167 #define dst_hi dst[1]
168 #define src_lo src[0]
169 #define src_hi src[1]
171 #define STACK_ALIGNMENT 8
173 * Stack space for BPF_REG_1, BPF_REG_2, BPF_REG_3, BPF_REG_4,
174 * BPF_REG_5, BPF_REG_6, BPF_REG_7, BPF_REG_8, BPF_REG_9,
175 * BPF_REG_FP, BPF_REG_AX and Tail call counts.
177 #define SCRATCH_SIZE 96
179 /* Total stack size used in JITed code */
180 #define _STACK_SIZE (stack_depth + SCRATCH_SIZE)
182 #define STACK_SIZE ALIGN(_STACK_SIZE, STACK_ALIGNMENT)
184 /* Get the offset of eBPF REGISTERs stored on scratch space. */
185 #define STACK_VAR(off) (off)
187 /* Encode 'dst_reg' register into IA32 opcode 'byte' */
188 static u8 add_1reg(u8 byte, u32 dst_reg)
190 return byte + dst_reg;
193 /* Encode 'dst_reg' and 'src_reg' registers into IA32 opcode 'byte' */
194 static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg)
196 return byte + dst_reg + (src_reg << 3);
199 static void jit_fill_hole(void *area, unsigned int size)
201 /* Fill whole space with int3 instructions */
202 memset(area, 0xcc, size);
205 static inline void emit_ia32_mov_i(const u8 dst, const u32 val, bool dstk,
214 EMIT2(0x33, add_2reg(0xC0, IA32_EAX, IA32_EAX));
215 /* mov dword ptr [ebp+off],eax */
216 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
219 EMIT3_off32(0xC7, add_1reg(0x40, IA32_EBP),
220 STACK_VAR(dst), val);
224 EMIT2(0x33, add_2reg(0xC0, dst, dst));
226 EMIT2_off32(0xC7, add_1reg(0xC0, dst),
232 /* dst = imm (4 bytes)*/
233 static inline void emit_ia32_mov_r(const u8 dst, const u8 src, bool dstk,
234 bool sstk, u8 **pprog)
238 u8 sreg = sstk ? IA32_EAX : src;
241 /* mov eax,dword ptr [ebp+off] */
242 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(src));
244 /* mov dword ptr [ebp+off],eax */
245 EMIT3(0x89, add_2reg(0x40, IA32_EBP, sreg), STACK_VAR(dst));
248 EMIT2(0x89, add_2reg(0xC0, dst, sreg));
254 static inline void emit_ia32_mov_r64(const bool is64, const u8 dst[],
255 const u8 src[], bool dstk,
256 bool sstk, u8 **pprog,
257 const struct bpf_prog_aux *aux)
259 emit_ia32_mov_r(dst_lo, src_lo, dstk, sstk, pprog);
261 /* complete 8 byte move */
262 emit_ia32_mov_r(dst_hi, src_hi, dstk, sstk, pprog);
263 else if (!aux->verifier_zext)
264 /* zero out high 4 bytes */
265 emit_ia32_mov_i(dst_hi, 0, dstk, pprog);
268 /* Sign extended move */
269 static inline void emit_ia32_mov_i64(const bool is64, const u8 dst[],
270 const u32 val, bool dstk, u8 **pprog)
274 if (is64 && (val & (1<<31)))
276 emit_ia32_mov_i(dst_lo, val, dstk, pprog);
277 emit_ia32_mov_i(dst_hi, hi, dstk, pprog);
281 * ALU operation (32 bit)
284 static inline void emit_ia32_mul_r(const u8 dst, const u8 src, bool dstk,
285 bool sstk, u8 **pprog)
289 u8 sreg = sstk ? IA32_ECX : src;
292 /* mov ecx,dword ptr [ebp+off] */
293 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src));
296 /* mov eax,dword ptr [ebp+off] */
297 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(dst));
300 EMIT2(0x8B, add_2reg(0xC0, dst, IA32_EAX));
303 EMIT2(0xF7, add_1reg(0xE0, sreg));
306 /* mov dword ptr [ebp+off],eax */
307 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
311 EMIT2(0x89, add_2reg(0xC0, dst, IA32_EAX));
316 static inline void emit_ia32_to_le_r64(const u8 dst[], s32 val,
317 bool dstk, u8 **pprog,
318 const struct bpf_prog_aux *aux)
322 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
323 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
325 if (dstk && val != 64) {
326 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
328 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
334 * Emit 'movzwl eax,ax' to zero extend 16-bit
338 EMIT1(add_2reg(0xC0, dreg_lo, dreg_lo));
339 if (!aux->verifier_zext)
340 /* xor dreg_hi,dreg_hi */
341 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
344 if (!aux->verifier_zext)
345 /* xor dreg_hi,dreg_hi */
346 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
353 if (dstk && val != 64) {
354 /* mov dword ptr [ebp+off],dreg_lo */
355 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
357 /* mov dword ptr [ebp+off],dreg_hi */
358 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
364 static inline void emit_ia32_to_be_r64(const u8 dst[], s32 val,
365 bool dstk, u8 **pprog,
366 const struct bpf_prog_aux *aux)
370 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
371 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
374 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
376 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
381 /* Emit 'ror %ax, 8' to swap lower 2 bytes */
383 EMIT3(0xC1, add_1reg(0xC8, dreg_lo), 8);
386 EMIT1(add_2reg(0xC0, dreg_lo, dreg_lo));
388 if (!aux->verifier_zext)
389 /* xor dreg_hi,dreg_hi */
390 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
393 /* Emit 'bswap eax' to swap lower 4 bytes */
395 EMIT1(add_1reg(0xC8, dreg_lo));
397 if (!aux->verifier_zext)
398 /* xor dreg_hi,dreg_hi */
399 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
402 /* Emit 'bswap eax' to swap lower 4 bytes */
404 EMIT1(add_1reg(0xC8, dreg_lo));
406 /* Emit 'bswap edx' to swap lower 4 bytes */
408 EMIT1(add_1reg(0xC8, dreg_hi));
410 /* mov ecx,dreg_hi */
411 EMIT2(0x89, add_2reg(0xC0, IA32_ECX, dreg_hi));
412 /* mov dreg_hi,dreg_lo */
413 EMIT2(0x89, add_2reg(0xC0, dreg_hi, dreg_lo));
414 /* mov dreg_lo,ecx */
415 EMIT2(0x89, add_2reg(0xC0, dreg_lo, IA32_ECX));
420 /* mov dword ptr [ebp+off],dreg_lo */
421 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
423 /* mov dword ptr [ebp+off],dreg_hi */
424 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
431 * ALU operation (32 bit)
432 * dst = dst (div|mod) src
434 static inline void emit_ia32_div_mod_r(const u8 op, const u8 dst, const u8 src,
435 bool dstk, bool sstk, u8 **pprog)
441 /* mov ecx,dword ptr [ebp+off] */
442 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
444 else if (src != IA32_ECX)
446 EMIT2(0x8B, add_2reg(0xC0, src, IA32_ECX));
449 /* mov eax,dword ptr [ebp+off] */
450 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
454 EMIT2(0x8B, add_2reg(0xC0, dst, IA32_EAX));
457 EMIT2(0x31, add_2reg(0xC0, IA32_EDX, IA32_EDX));
459 EMIT2(0xF7, add_1reg(0xF0, IA32_ECX));
463 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX),
466 EMIT2(0x89, add_2reg(0xC0, dst, IA32_EDX));
469 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
472 EMIT2(0x89, add_2reg(0xC0, dst, IA32_EAX));
478 * ALU operation (32 bit)
479 * dst = dst (shift) src
481 static inline void emit_ia32_shift_r(const u8 op, const u8 dst, const u8 src,
482 bool dstk, bool sstk, u8 **pprog)
486 u8 dreg = dstk ? IA32_EAX : dst;
490 /* mov eax,dword ptr [ebp+off] */
491 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(dst));
494 /* mov ecx,dword ptr [ebp+off] */
495 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src));
496 else if (src != IA32_ECX)
498 EMIT2(0x8B, add_2reg(0xC0, src, IA32_ECX));
510 EMIT2(0xD3, add_1reg(b2, dreg));
513 /* mov dword ptr [ebp+off],dreg */
514 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg), STACK_VAR(dst));
519 * ALU operation (32 bit)
522 static inline void emit_ia32_alu_r(const bool is64, const bool hi, const u8 op,
523 const u8 dst, const u8 src, bool dstk,
524 bool sstk, u8 **pprog)
528 u8 sreg = sstk ? IA32_EAX : src;
529 u8 dreg = dstk ? IA32_EDX : dst;
532 /* mov eax,dword ptr [ebp+off] */
533 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(src));
536 /* mov eax,dword ptr [ebp+off] */
537 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), STACK_VAR(dst));
539 switch (BPF_OP(op)) {
540 /* dst = dst + src */
543 EMIT2(0x11, add_2reg(0xC0, dreg, sreg));
545 EMIT2(0x01, add_2reg(0xC0, dreg, sreg));
547 /* dst = dst - src */
550 EMIT2(0x19, add_2reg(0xC0, dreg, sreg));
552 EMIT2(0x29, add_2reg(0xC0, dreg, sreg));
554 /* dst = dst | src */
556 EMIT2(0x09, add_2reg(0xC0, dreg, sreg));
558 /* dst = dst & src */
560 EMIT2(0x21, add_2reg(0xC0, dreg, sreg));
562 /* dst = dst ^ src */
564 EMIT2(0x31, add_2reg(0xC0, dreg, sreg));
569 /* mov dword ptr [ebp+off],dreg */
570 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg),
575 /* ALU operation (64 bit) */
576 static inline void emit_ia32_alu_r64(const bool is64, const u8 op,
577 const u8 dst[], const u8 src[],
578 bool dstk, bool sstk,
579 u8 **pprog, const struct bpf_prog_aux *aux)
583 emit_ia32_alu_r(is64, false, op, dst_lo, src_lo, dstk, sstk, &prog);
585 emit_ia32_alu_r(is64, true, op, dst_hi, src_hi, dstk, sstk,
587 else if (!aux->verifier_zext)
588 emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
593 * ALU operation (32 bit)
596 static inline void emit_ia32_alu_i(const bool is64, const bool hi, const u8 op,
597 const u8 dst, const s32 val, bool dstk,
602 u8 dreg = dstk ? IA32_EAX : dst;
606 /* mov eax,dword ptr [ebp+off] */
607 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(dst));
611 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EDX), val);
614 /* dst = dst + val */
618 EMIT3(0x83, add_1reg(0xD0, dreg), val);
620 EMIT2(0x11, add_2reg(0xC0, dreg, sreg));
623 EMIT3(0x83, add_1reg(0xC0, dreg), val);
625 EMIT2(0x01, add_2reg(0xC0, dreg, sreg));
628 /* dst = dst - val */
632 EMIT3(0x83, add_1reg(0xD8, dreg), val);
634 EMIT2(0x19, add_2reg(0xC0, dreg, sreg));
637 EMIT3(0x83, add_1reg(0xE8, dreg), val);
639 EMIT2(0x29, add_2reg(0xC0, dreg, sreg));
642 /* dst = dst | val */
645 EMIT3(0x83, add_1reg(0xC8, dreg), val);
647 EMIT2(0x09, add_2reg(0xC0, dreg, sreg));
649 /* dst = dst & val */
652 EMIT3(0x83, add_1reg(0xE0, dreg), val);
654 EMIT2(0x21, add_2reg(0xC0, dreg, sreg));
656 /* dst = dst ^ val */
659 EMIT3(0x83, add_1reg(0xF0, dreg), val);
661 EMIT2(0x31, add_2reg(0xC0, dreg, sreg));
664 EMIT2(0xF7, add_1reg(0xD8, dreg));
669 /* mov dword ptr [ebp+off],dreg */
670 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg),
675 /* ALU operation (64 bit) */
676 static inline void emit_ia32_alu_i64(const bool is64, const u8 op,
677 const u8 dst[], const u32 val,
678 bool dstk, u8 **pprog,
679 const struct bpf_prog_aux *aux)
684 if (is64 && (val & (1<<31)))
687 emit_ia32_alu_i(is64, false, op, dst_lo, val, dstk, &prog);
689 emit_ia32_alu_i(is64, true, op, dst_hi, hi, dstk, &prog);
690 else if (!aux->verifier_zext)
691 emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
696 /* dst = ~dst (64 bit) */
697 static inline void emit_ia32_neg64(const u8 dst[], bool dstk, u8 **pprog)
701 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
702 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
705 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
707 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
712 EMIT2(0xF7, add_1reg(0xD8, dreg_lo));
713 /* adc dreg_hi,0x0 */
714 EMIT3(0x83, add_1reg(0xD0, dreg_hi), 0x00);
716 EMIT2(0xF7, add_1reg(0xD8, dreg_hi));
719 /* mov dword ptr [ebp+off],dreg_lo */
720 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
722 /* mov dword ptr [ebp+off],dreg_hi */
723 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
729 /* dst = dst << src */
730 static inline void emit_ia32_lsh_r64(const u8 dst[], const u8 src[],
731 bool dstk, bool sstk, u8 **pprog)
735 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
736 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
739 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
741 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
746 /* mov ecx,dword ptr [ebp+off] */
747 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
751 EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_ECX));
753 /* shld dreg_hi,dreg_lo,cl */
754 EMIT3(0x0F, 0xA5, add_2reg(0xC0, dreg_hi, dreg_lo));
756 EMIT2(0xD3, add_1reg(0xE0, dreg_lo));
758 /* if ecx >= 32, mov dreg_lo into dreg_hi and clear dreg_lo */
761 EMIT3(0x83, add_1reg(0xF8, IA32_ECX), 32);
762 /* skip the next two instructions (4 bytes) when < 32 */
765 /* mov dreg_hi,dreg_lo */
766 EMIT2(0x89, add_2reg(0xC0, dreg_hi, dreg_lo));
767 /* xor dreg_lo,dreg_lo */
768 EMIT2(0x33, add_2reg(0xC0, dreg_lo, dreg_lo));
771 /* mov dword ptr [ebp+off],dreg_lo */
772 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
774 /* mov dword ptr [ebp+off],dreg_hi */
775 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
782 /* dst = dst >> src (signed)*/
783 static inline void emit_ia32_arsh_r64(const u8 dst[], const u8 src[],
784 bool dstk, bool sstk, u8 **pprog)
788 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
789 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
792 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
794 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
799 /* mov ecx,dword ptr [ebp+off] */
800 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
804 EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_ECX));
806 /* shrd dreg_lo,dreg_hi,cl */
807 EMIT3(0x0F, 0xAD, add_2reg(0xC0, dreg_lo, dreg_hi));
809 EMIT2(0xD3, add_1reg(0xF8, dreg_hi));
811 /* if ecx >= 32, mov dreg_hi to dreg_lo and set/clear dreg_hi depending on sign */
814 EMIT3(0x83, add_1reg(0xF8, IA32_ECX), 32);
815 /* skip the next two instructions (5 bytes) when < 32 */
818 /* mov dreg_lo,dreg_hi */
819 EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
821 EMIT3(0xC1, add_1reg(0xF8, dreg_hi), 31);
824 /* mov dword ptr [ebp+off],dreg_lo */
825 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
827 /* mov dword ptr [ebp+off],dreg_hi */
828 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
835 /* dst = dst >> src */
836 static inline void emit_ia32_rsh_r64(const u8 dst[], const u8 src[], bool dstk,
837 bool sstk, u8 **pprog)
841 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
842 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
845 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
847 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
852 /* mov ecx,dword ptr [ebp+off] */
853 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
857 EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_ECX));
859 /* shrd dreg_lo,dreg_hi,cl */
860 EMIT3(0x0F, 0xAD, add_2reg(0xC0, dreg_lo, dreg_hi));
862 EMIT2(0xD3, add_1reg(0xE8, dreg_hi));
864 /* if ecx >= 32, mov dreg_hi to dreg_lo and clear dreg_hi */
867 EMIT3(0x83, add_1reg(0xF8, IA32_ECX), 32);
868 /* skip the next two instructions (4 bytes) when < 32 */
871 /* mov dreg_lo,dreg_hi */
872 EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
873 /* xor dreg_hi,dreg_hi */
874 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
877 /* mov dword ptr [ebp+off],dreg_lo */
878 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
880 /* mov dword ptr [ebp+off],dreg_hi */
881 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
888 /* dst = dst << val */
889 static inline void emit_ia32_lsh_i64(const u8 dst[], const u32 val,
890 bool dstk, u8 **pprog)
894 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
895 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
898 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
900 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
903 /* Do LSH operation */
905 /* shld dreg_hi,dreg_lo,imm8 */
906 EMIT4(0x0F, 0xA4, add_2reg(0xC0, dreg_hi, dreg_lo), val);
907 /* shl dreg_lo,imm8 */
908 EMIT3(0xC1, add_1reg(0xE0, dreg_lo), val);
909 } else if (val >= 32 && val < 64) {
910 u32 value = val - 32;
912 /* shl dreg_lo,imm8 */
913 EMIT3(0xC1, add_1reg(0xE0, dreg_lo), value);
914 /* mov dreg_hi,dreg_lo */
915 EMIT2(0x89, add_2reg(0xC0, dreg_hi, dreg_lo));
916 /* xor dreg_lo,dreg_lo */
917 EMIT2(0x33, add_2reg(0xC0, dreg_lo, dreg_lo));
919 /* xor dreg_lo,dreg_lo */
920 EMIT2(0x33, add_2reg(0xC0, dreg_lo, dreg_lo));
921 /* xor dreg_hi,dreg_hi */
922 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
926 /* mov dword ptr [ebp+off],dreg_lo */
927 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
929 /* mov dword ptr [ebp+off],dreg_hi */
930 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
936 /* dst = dst >> val */
937 static inline void emit_ia32_rsh_i64(const u8 dst[], const u32 val,
938 bool dstk, u8 **pprog)
942 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
943 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
946 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
948 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
952 /* Do RSH operation */
954 /* shrd dreg_lo,dreg_hi,imm8 */
955 EMIT4(0x0F, 0xAC, add_2reg(0xC0, dreg_lo, dreg_hi), val);
956 /* shr dreg_hi,imm8 */
957 EMIT3(0xC1, add_1reg(0xE8, dreg_hi), val);
958 } else if (val >= 32 && val < 64) {
959 u32 value = val - 32;
961 /* shr dreg_hi,imm8 */
962 EMIT3(0xC1, add_1reg(0xE8, dreg_hi), value);
963 /* mov dreg_lo,dreg_hi */
964 EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
965 /* xor dreg_hi,dreg_hi */
966 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
968 /* xor dreg_lo,dreg_lo */
969 EMIT2(0x33, add_2reg(0xC0, dreg_lo, dreg_lo));
970 /* xor dreg_hi,dreg_hi */
971 EMIT2(0x33, add_2reg(0xC0, dreg_hi, dreg_hi));
975 /* mov dword ptr [ebp+off],dreg_lo */
976 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
978 /* mov dword ptr [ebp+off],dreg_hi */
979 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
985 /* dst = dst >> val (signed) */
986 static inline void emit_ia32_arsh_i64(const u8 dst[], const u32 val,
987 bool dstk, u8 **pprog)
991 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
992 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
995 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
997 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
1000 /* Do RSH operation */
1002 /* shrd dreg_lo,dreg_hi,imm8 */
1003 EMIT4(0x0F, 0xAC, add_2reg(0xC0, dreg_lo, dreg_hi), val);
1004 /* ashr dreg_hi,imm8 */
1005 EMIT3(0xC1, add_1reg(0xF8, dreg_hi), val);
1006 } else if (val >= 32 && val < 64) {
1007 u32 value = val - 32;
1009 /* ashr dreg_hi,imm8 */
1010 EMIT3(0xC1, add_1reg(0xF8, dreg_hi), value);
1011 /* mov dreg_lo,dreg_hi */
1012 EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
1014 /* ashr dreg_hi,imm8 */
1015 EMIT3(0xC1, add_1reg(0xF8, dreg_hi), 31);
1017 /* ashr dreg_hi,imm8 */
1018 EMIT3(0xC1, add_1reg(0xF8, dreg_hi), 31);
1019 /* mov dreg_lo,dreg_hi */
1020 EMIT2(0x89, add_2reg(0xC0, dreg_lo, dreg_hi));
1024 /* mov dword ptr [ebp+off],dreg_lo */
1025 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_lo),
1027 /* mov dword ptr [ebp+off],dreg_hi */
1028 EMIT3(0x89, add_2reg(0x40, IA32_EBP, dreg_hi),
1034 static inline void emit_ia32_mul_r64(const u8 dst[], const u8 src[], bool dstk,
1035 bool sstk, u8 **pprog)
1041 /* mov eax,dword ptr [ebp+off] */
1042 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1045 /* mov eax,dst_hi */
1046 EMIT2(0x8B, add_2reg(0xC0, dst_hi, IA32_EAX));
1049 /* mul dword ptr [ebp+off] */
1050 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(src_lo));
1053 EMIT2(0xF7, add_1reg(0xE0, src_lo));
1056 EMIT2(0x89, add_2reg(0xC0, IA32_ECX, IA32_EAX));
1059 /* mov eax,dword ptr [ebp+off] */
1060 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1063 /* mov eax,dst_lo */
1064 EMIT2(0x8B, add_2reg(0xC0, dst_lo, IA32_EAX));
1067 /* mul dword ptr [ebp+off] */
1068 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(src_hi));
1071 EMIT2(0xF7, add_1reg(0xE0, src_hi));
1074 EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EAX));
1077 /* mov eax,dword ptr [ebp+off] */
1078 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1081 /* mov eax,dst_lo */
1082 EMIT2(0x8B, add_2reg(0xC0, dst_lo, IA32_EAX));
1085 /* mul dword ptr [ebp+off] */
1086 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(src_lo));
1089 EMIT2(0xF7, add_1reg(0xE0, src_lo));
1092 EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EDX));
1095 /* mov dword ptr [ebp+off],eax */
1096 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
1098 /* mov dword ptr [ebp+off],ecx */
1099 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_ECX),
1102 /* mov dst_lo,eax */
1103 EMIT2(0x89, add_2reg(0xC0, dst_lo, IA32_EAX));
1104 /* mov dst_hi,ecx */
1105 EMIT2(0x89, add_2reg(0xC0, dst_hi, IA32_ECX));
1111 static inline void emit_ia32_mul_i64(const u8 dst[], const u32 val,
1112 bool dstk, u8 **pprog)
1118 hi = val & (1<<31) ? (u32)~0 : 0;
1119 /* movl eax,imm32 */
1120 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), val);
1122 /* mul dword ptr [ebp+off] */
1123 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(dst_hi));
1126 EMIT2(0xF7, add_1reg(0xE0, dst_hi));
1129 EMIT2(0x89, add_2reg(0xC0, IA32_ECX, IA32_EAX));
1131 /* movl eax,imm32 */
1132 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), hi);
1134 /* mul dword ptr [ebp+off] */
1135 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(dst_lo));
1138 EMIT2(0xF7, add_1reg(0xE0, dst_lo));
1140 EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EAX));
1142 /* movl eax,imm32 */
1143 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), val);
1145 /* mul dword ptr [ebp+off] */
1146 EMIT3(0xF7, add_1reg(0x60, IA32_EBP), STACK_VAR(dst_lo));
1149 EMIT2(0xF7, add_1reg(0xE0, dst_lo));
1152 EMIT2(0x01, add_2reg(0xC0, IA32_ECX, IA32_EDX));
1155 /* mov dword ptr [ebp+off],eax */
1156 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
1158 /* mov dword ptr [ebp+off],ecx */
1159 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_ECX),
1162 /* mov dword ptr [ebp+off],eax */
1163 EMIT2(0x89, add_2reg(0xC0, dst_lo, IA32_EAX));
1164 /* mov dword ptr [ebp+off],ecx */
1165 EMIT2(0x89, add_2reg(0xC0, dst_hi, IA32_ECX));
1171 static int bpf_size_to_x86_bytes(int bpf_size)
1173 if (bpf_size == BPF_W)
1175 else if (bpf_size == BPF_H)
1177 else if (bpf_size == BPF_B)
1179 else if (bpf_size == BPF_DW)
1180 return 4; /* imm32 */
1185 struct jit_context {
1186 int cleanup_addr; /* Epilogue code offset */
1189 /* Maximum number of bytes emitted while JITing one eBPF insn */
1190 #define BPF_MAX_INSN_SIZE 128
1191 #define BPF_INSN_SAFETY 64
1193 #define PROLOGUE_SIZE 35
1196 * Emit prologue code for BPF program and check it's size.
1197 * bpf_tail_call helper will skip it while jumping into another program.
1199 static void emit_prologue(u8 **pprog, u32 stack_depth)
1203 const u8 *r1 = bpf2ia32[BPF_REG_1];
1204 const u8 fplo = bpf2ia32[BPF_REG_FP][0];
1205 const u8 fphi = bpf2ia32[BPF_REG_FP][1];
1206 const u8 *tcc = bpf2ia32[TCALL_CNT];
1219 /* sub esp,STACK_SIZE */
1220 EMIT2_off32(0x81, 0xEC, STACK_SIZE);
1221 /* sub ebp,SCRATCH_SIZE+12*/
1222 EMIT3(0x83, add_1reg(0xE8, IA32_EBP), SCRATCH_SIZE + 12);
1224 EMIT2(0x31, add_2reg(0xC0, IA32_EBX, IA32_EBX));
1226 /* Set up BPF prog stack base register */
1227 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBP), STACK_VAR(fplo));
1228 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(fphi));
1230 /* Move BPF_CTX (EAX) to BPF_REG_R1 */
1231 /* mov dword ptr [ebp+off],eax */
1232 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r1[0]));
1233 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(r1[1]));
1235 /* Initialize Tail Count */
1236 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[0]));
1237 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[1]));
1239 BUILD_BUG_ON(cnt != PROLOGUE_SIZE);
1243 /* Emit epilogue code for BPF program */
1244 static void emit_epilogue(u8 **pprog, u32 stack_depth)
1247 const u8 *r0 = bpf2ia32[BPF_REG_0];
1250 /* mov eax,dword ptr [ebp+off]*/
1251 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r0[0]));
1252 /* mov edx,dword ptr [ebp+off]*/
1253 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), STACK_VAR(r0[1]));
1255 /* add ebp,SCRATCH_SIZE+12*/
1256 EMIT3(0x83, add_1reg(0xC0, IA32_EBP), SCRATCH_SIZE + 12);
1258 /* mov ebx,dword ptr [ebp-12]*/
1259 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EBX), -12);
1260 /* mov esi,dword ptr [ebp-8]*/
1261 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ESI), -8);
1262 /* mov edi,dword ptr [ebp-4]*/
1263 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDI), -4);
1265 EMIT1(0xC9); /* leave */
1266 EMIT1(0xC3); /* ret */
1271 * Generate the following code:
1272 * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ...
1273 * if (index >= array->map.max_entries)
1275 * if (++tail_call_cnt > MAX_TAIL_CALL_CNT)
1277 * prog = array->ptrs[index];
1280 * goto *(prog->bpf_func + prologue_size);
1283 static void emit_bpf_tail_call(u8 **pprog)
1287 const u8 *r1 = bpf2ia32[BPF_REG_1];
1288 const u8 *r2 = bpf2ia32[BPF_REG_2];
1289 const u8 *r3 = bpf2ia32[BPF_REG_3];
1290 const u8 *tcc = bpf2ia32[TCALL_CNT];
1292 static int jmp_label1 = -1;
1295 * if (index >= array->map.max_entries)
1298 /* mov eax,dword ptr [ebp+off] */
1299 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r2[0]));
1300 /* mov edx,dword ptr [ebp+off] */
1301 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX), STACK_VAR(r3[0]));
1303 /* cmp dword ptr [eax+off],edx */
1304 EMIT3(0x39, add_2reg(0x40, IA32_EAX, IA32_EDX),
1305 offsetof(struct bpf_array, map.max_entries));
1307 EMIT2(IA32_JBE, jmp_label(jmp_label1, 2));
1310 * if (tail_call_cnt > MAX_TAIL_CALL_CNT)
1313 lo = (u32)MAX_TAIL_CALL_CNT;
1314 hi = (u32)((u64)MAX_TAIL_CALL_CNT >> 32);
1315 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(tcc[0]));
1316 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[1]));
1319 EMIT3(0x83, add_1reg(0xF8, IA32_EBX), hi);
1322 EMIT3(0x83, add_1reg(0xF8, IA32_ECX), lo);
1325 EMIT2(IA32_JAE, jmp_label(jmp_label1, 2));
1328 EMIT3(0x83, add_1reg(0xC0, IA32_ECX), 0x01);
1330 EMIT3(0x83, add_1reg(0xD0, IA32_EBX), 0x00);
1332 /* mov dword ptr [ebp+off],eax */
1333 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(tcc[0]));
1334 /* mov dword ptr [ebp+off],edx */
1335 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EBX), STACK_VAR(tcc[1]));
1337 /* prog = array->ptrs[index]; */
1338 /* mov edx, [eax + edx * 4 + offsetof(...)] */
1339 EMIT3_off32(0x8B, 0x94, 0x90, offsetof(struct bpf_array, ptrs));
1346 EMIT2(0x85, add_2reg(0xC0, IA32_EDX, IA32_EDX));
1348 EMIT2(IA32_JE, jmp_label(jmp_label1, 2));
1350 /* goto *(prog->bpf_func + prologue_size); */
1351 /* mov edx, dword ptr [edx + 32] */
1352 EMIT3(0x8B, add_2reg(0x40, IA32_EDX, IA32_EDX),
1353 offsetof(struct bpf_prog, bpf_func));
1354 /* add edx,prologue_size */
1355 EMIT3(0x83, add_1reg(0xC0, IA32_EDX), PROLOGUE_SIZE);
1357 /* mov eax,dword ptr [ebp+off] */
1358 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX), STACK_VAR(r1[0]));
1361 * Now we're ready to jump into next BPF program:
1362 * eax == ctx (1st arg)
1363 * edx == prog->bpf_func + prologue_size
1365 RETPOLINE_EDX_BPF_JIT();
1367 if (jmp_label1 == -1)
1374 /* Push the scratch stack register on top of the stack. */
1375 static inline void emit_push_r64(const u8 src[], u8 **pprog)
1380 /* mov ecx,dword ptr [ebp+off] */
1381 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src_hi));
1385 /* mov ecx,dword ptr [ebp+off] */
1386 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX), STACK_VAR(src_lo));
1393 static u8 get_cond_jmp_opcode(const u8 op, bool is_cmp_lo)
1397 /* Convert BPF opcode to x86 */
1404 jmp_cond = IA32_JNE;
1407 /* GT is unsigned '>', JA in x86 */
1411 /* LT is unsigned '<', JB in x86 */
1415 /* GE is unsigned '>=', JAE in x86 */
1416 jmp_cond = IA32_JAE;
1419 /* LE is unsigned '<=', JBE in x86 */
1420 jmp_cond = IA32_JBE;
1424 /* Signed '>', GT in x86 */
1427 /* GT is unsigned '>', JA in x86 */
1432 /* Signed '<', LT in x86 */
1435 /* LT is unsigned '<', JB in x86 */
1440 /* Signed '>=', GE in x86 */
1441 jmp_cond = IA32_JGE;
1443 /* GE is unsigned '>=', JAE in x86 */
1444 jmp_cond = IA32_JAE;
1448 /* Signed '<=', LE in x86 */
1449 jmp_cond = IA32_JLE;
1451 /* LE is unsigned '<=', JBE in x86 */
1452 jmp_cond = IA32_JBE;
1454 default: /* to silence GCC warning */
1455 jmp_cond = COND_JMP_OPCODE_INVALID;
1462 static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image,
1463 int oldproglen, struct jit_context *ctx)
1465 struct bpf_insn *insn = bpf_prog->insnsi;
1466 int insn_cnt = bpf_prog->len;
1467 bool seen_exit = false;
1468 u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY];
1473 emit_prologue(&prog, bpf_prog->aux->stack_depth);
1475 for (i = 0; i < insn_cnt; i++, insn++) {
1476 const s32 imm32 = insn->imm;
1477 const bool is64 = BPF_CLASS(insn->code) == BPF_ALU64;
1478 const bool dstk = insn->dst_reg == BPF_REG_AX ? false : true;
1479 const bool sstk = insn->src_reg == BPF_REG_AX ? false : true;
1480 const u8 code = insn->code;
1481 const u8 *dst = bpf2ia32[insn->dst_reg];
1482 const u8 *src = bpf2ia32[insn->src_reg];
1483 const u8 *r0 = bpf2ia32[BPF_REG_0];
1490 /* ALU operations */
1492 case BPF_ALU | BPF_MOV | BPF_K:
1493 case BPF_ALU | BPF_MOV | BPF_X:
1494 case BPF_ALU64 | BPF_MOV | BPF_K:
1495 case BPF_ALU64 | BPF_MOV | BPF_X:
1496 switch (BPF_SRC(code)) {
1499 /* Special mov32 for zext. */
1500 emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
1503 emit_ia32_mov_r64(is64, dst, src, dstk, sstk,
1504 &prog, bpf_prog->aux);
1507 /* Sign-extend immediate value to dst reg */
1508 emit_ia32_mov_i64(is64, dst, imm32,
1513 /* dst = dst + src/imm */
1514 /* dst = dst - src/imm */
1515 /* dst = dst | src/imm */
1516 /* dst = dst & src/imm */
1517 /* dst = dst ^ src/imm */
1518 /* dst = dst * src/imm */
1519 /* dst = dst << src */
1520 /* dst = dst >> src */
1521 case BPF_ALU | BPF_ADD | BPF_K:
1522 case BPF_ALU | BPF_ADD | BPF_X:
1523 case BPF_ALU | BPF_SUB | BPF_K:
1524 case BPF_ALU | BPF_SUB | BPF_X:
1525 case BPF_ALU | BPF_OR | BPF_K:
1526 case BPF_ALU | BPF_OR | BPF_X:
1527 case BPF_ALU | BPF_AND | BPF_K:
1528 case BPF_ALU | BPF_AND | BPF_X:
1529 case BPF_ALU | BPF_XOR | BPF_K:
1530 case BPF_ALU | BPF_XOR | BPF_X:
1531 case BPF_ALU64 | BPF_ADD | BPF_K:
1532 case BPF_ALU64 | BPF_ADD | BPF_X:
1533 case BPF_ALU64 | BPF_SUB | BPF_K:
1534 case BPF_ALU64 | BPF_SUB | BPF_X:
1535 case BPF_ALU64 | BPF_OR | BPF_K:
1536 case BPF_ALU64 | BPF_OR | BPF_X:
1537 case BPF_ALU64 | BPF_AND | BPF_K:
1538 case BPF_ALU64 | BPF_AND | BPF_X:
1539 case BPF_ALU64 | BPF_XOR | BPF_K:
1540 case BPF_ALU64 | BPF_XOR | BPF_X:
1541 switch (BPF_SRC(code)) {
1543 emit_ia32_alu_r64(is64, BPF_OP(code), dst,
1544 src, dstk, sstk, &prog,
1548 emit_ia32_alu_i64(is64, BPF_OP(code), dst,
1554 case BPF_ALU | BPF_MUL | BPF_K:
1555 case BPF_ALU | BPF_MUL | BPF_X:
1556 switch (BPF_SRC(code)) {
1558 emit_ia32_mul_r(dst_lo, src_lo, dstk,
1563 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX),
1565 emit_ia32_mul_r(dst_lo, IA32_ECX, dstk,
1569 if (!bpf_prog->aux->verifier_zext)
1570 emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
1572 case BPF_ALU | BPF_LSH | BPF_X:
1573 case BPF_ALU | BPF_RSH | BPF_X:
1574 case BPF_ALU | BPF_ARSH | BPF_K:
1575 case BPF_ALU | BPF_ARSH | BPF_X:
1576 switch (BPF_SRC(code)) {
1578 emit_ia32_shift_r(BPF_OP(code), dst_lo, src_lo,
1583 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX),
1585 emit_ia32_shift_r(BPF_OP(code), dst_lo,
1586 IA32_ECX, dstk, false,
1590 if (!bpf_prog->aux->verifier_zext)
1591 emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
1593 /* dst = dst / src(imm) */
1594 /* dst = dst % src(imm) */
1595 case BPF_ALU | BPF_DIV | BPF_K:
1596 case BPF_ALU | BPF_DIV | BPF_X:
1597 case BPF_ALU | BPF_MOD | BPF_K:
1598 case BPF_ALU | BPF_MOD | BPF_X:
1599 switch (BPF_SRC(code)) {
1601 emit_ia32_div_mod_r(BPF_OP(code), dst_lo,
1602 src_lo, dstk, sstk, &prog);
1606 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX),
1608 emit_ia32_div_mod_r(BPF_OP(code), dst_lo,
1609 IA32_ECX, dstk, false,
1613 if (!bpf_prog->aux->verifier_zext)
1614 emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
1616 case BPF_ALU64 | BPF_DIV | BPF_K:
1617 case BPF_ALU64 | BPF_DIV | BPF_X:
1618 case BPF_ALU64 | BPF_MOD | BPF_K:
1619 case BPF_ALU64 | BPF_MOD | BPF_X:
1621 /* dst = dst >> imm */
1622 /* dst = dst << imm */
1623 case BPF_ALU | BPF_RSH | BPF_K:
1624 case BPF_ALU | BPF_LSH | BPF_K:
1625 if (unlikely(imm32 > 31))
1628 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), imm32);
1629 emit_ia32_shift_r(BPF_OP(code), dst_lo, IA32_ECX, dstk,
1631 if (!bpf_prog->aux->verifier_zext)
1632 emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
1634 /* dst = dst << imm */
1635 case BPF_ALU64 | BPF_LSH | BPF_K:
1636 if (unlikely(imm32 > 63))
1638 emit_ia32_lsh_i64(dst, imm32, dstk, &prog);
1640 /* dst = dst >> imm */
1641 case BPF_ALU64 | BPF_RSH | BPF_K:
1642 if (unlikely(imm32 > 63))
1644 emit_ia32_rsh_i64(dst, imm32, dstk, &prog);
1646 /* dst = dst << src */
1647 case BPF_ALU64 | BPF_LSH | BPF_X:
1648 emit_ia32_lsh_r64(dst, src, dstk, sstk, &prog);
1650 /* dst = dst >> src */
1651 case BPF_ALU64 | BPF_RSH | BPF_X:
1652 emit_ia32_rsh_r64(dst, src, dstk, sstk, &prog);
1654 /* dst = dst >> src (signed) */
1655 case BPF_ALU64 | BPF_ARSH | BPF_X:
1656 emit_ia32_arsh_r64(dst, src, dstk, sstk, &prog);
1658 /* dst = dst >> imm (signed) */
1659 case BPF_ALU64 | BPF_ARSH | BPF_K:
1660 if (unlikely(imm32 > 63))
1662 emit_ia32_arsh_i64(dst, imm32, dstk, &prog);
1665 case BPF_ALU | BPF_NEG:
1666 emit_ia32_alu_i(is64, false, BPF_OP(code),
1667 dst_lo, 0, dstk, &prog);
1668 if (!bpf_prog->aux->verifier_zext)
1669 emit_ia32_mov_i(dst_hi, 0, dstk, &prog);
1671 /* dst = ~dst (64 bit) */
1672 case BPF_ALU64 | BPF_NEG:
1673 emit_ia32_neg64(dst, dstk, &prog);
1675 /* dst = dst * src/imm */
1676 case BPF_ALU64 | BPF_MUL | BPF_X:
1677 case BPF_ALU64 | BPF_MUL | BPF_K:
1678 switch (BPF_SRC(code)) {
1680 emit_ia32_mul_r64(dst, src, dstk, sstk, &prog);
1683 emit_ia32_mul_i64(dst, imm32, dstk, &prog);
1687 /* dst = htole(dst) */
1688 case BPF_ALU | BPF_END | BPF_FROM_LE:
1689 emit_ia32_to_le_r64(dst, imm32, dstk, &prog,
1692 /* dst = htobe(dst) */
1693 case BPF_ALU | BPF_END | BPF_FROM_BE:
1694 emit_ia32_to_be_r64(dst, imm32, dstk, &prog,
1698 case BPF_LD | BPF_IMM | BPF_DW: {
1702 emit_ia32_mov_i(dst_lo, lo, dstk, &prog);
1703 emit_ia32_mov_i(dst_hi, hi, dstk, &prog);
1708 /* speculation barrier */
1709 case BPF_ST | BPF_NOSPEC:
1710 if (boot_cpu_has(X86_FEATURE_XMM2))
1712 EMIT3(0x0F, 0xAE, 0xE8);
1714 /* ST: *(u8*)(dst_reg + off) = imm */
1715 case BPF_ST | BPF_MEM | BPF_H:
1716 case BPF_ST | BPF_MEM | BPF_B:
1717 case BPF_ST | BPF_MEM | BPF_W:
1718 case BPF_ST | BPF_MEM | BPF_DW:
1720 /* mov eax,dword ptr [ebp+off] */
1721 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1724 /* mov eax,dst_lo */
1725 EMIT2(0x8B, add_2reg(0xC0, dst_lo, IA32_EAX));
1727 switch (BPF_SIZE(code)) {
1729 EMIT(0xC6, 1); break;
1731 EMIT2(0x66, 0xC7); break;
1734 EMIT(0xC7, 1); break;
1737 if (is_imm8(insn->off))
1738 EMIT2(add_1reg(0x40, IA32_EAX), insn->off);
1740 EMIT1_off32(add_1reg(0x80, IA32_EAX),
1742 EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(code)));
1744 if (BPF_SIZE(code) == BPF_DW) {
1747 hi = imm32 & (1<<31) ? (u32)~0 : 0;
1748 EMIT2_off32(0xC7, add_1reg(0x80, IA32_EAX),
1754 /* STX: *(u8*)(dst_reg + off) = src_reg */
1755 case BPF_STX | BPF_MEM | BPF_B:
1756 case BPF_STX | BPF_MEM | BPF_H:
1757 case BPF_STX | BPF_MEM | BPF_W:
1758 case BPF_STX | BPF_MEM | BPF_DW:
1760 /* mov eax,dword ptr [ebp+off] */
1761 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1764 /* mov eax,dst_lo */
1765 EMIT2(0x8B, add_2reg(0xC0, dst_lo, IA32_EAX));
1768 /* mov edx,dword ptr [ebp+off] */
1769 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
1772 /* mov edx,src_lo */
1773 EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_EDX));
1775 switch (BPF_SIZE(code)) {
1777 EMIT(0x88, 1); break;
1779 EMIT2(0x66, 0x89); break;
1782 EMIT(0x89, 1); break;
1785 if (is_imm8(insn->off))
1786 EMIT2(add_2reg(0x40, IA32_EAX, IA32_EDX),
1789 EMIT1_off32(add_2reg(0x80, IA32_EAX, IA32_EDX),
1792 if (BPF_SIZE(code) == BPF_DW) {
1794 /* mov edi,dword ptr [ebp+off] */
1795 EMIT3(0x8B, add_2reg(0x40, IA32_EBP,
1799 /* mov edi,src_hi */
1800 EMIT2(0x8B, add_2reg(0xC0, src_hi,
1803 if (is_imm8(insn->off + 4)) {
1804 EMIT2(add_2reg(0x40, IA32_EAX,
1808 EMIT1(add_2reg(0x80, IA32_EAX,
1810 EMIT(insn->off + 4, 4);
1815 /* LDX: dst_reg = *(u8*)(src_reg + off) */
1816 case BPF_LDX | BPF_MEM | BPF_B:
1817 case BPF_LDX | BPF_MEM | BPF_H:
1818 case BPF_LDX | BPF_MEM | BPF_W:
1819 case BPF_LDX | BPF_MEM | BPF_DW:
1821 /* mov eax,dword ptr [ebp+off] */
1822 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1825 /* mov eax,dword ptr [ebp+off] */
1826 EMIT2(0x8B, add_2reg(0xC0, src_lo, IA32_EAX));
1828 switch (BPF_SIZE(code)) {
1830 EMIT2(0x0F, 0xB6); break;
1832 EMIT2(0x0F, 0xB7); break;
1835 EMIT(0x8B, 1); break;
1838 if (is_imm8(insn->off))
1839 EMIT2(add_2reg(0x40, IA32_EAX, IA32_EDX),
1842 EMIT1_off32(add_2reg(0x80, IA32_EAX, IA32_EDX),
1846 /* mov dword ptr [ebp+off],edx */
1847 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX),
1850 /* mov dst_lo,edx */
1851 EMIT2(0x89, add_2reg(0xC0, dst_lo, IA32_EDX));
1852 switch (BPF_SIZE(code)) {
1856 if (bpf_prog->aux->verifier_zext)
1859 EMIT3(0xC7, add_1reg(0x40, IA32_EBP),
1863 /* xor dst_hi,dst_hi */
1865 add_2reg(0xC0, dst_hi, dst_hi));
1870 add_2reg(0x80, IA32_EAX, IA32_EDX),
1874 add_2reg(0x40, IA32_EBP,
1879 add_2reg(0xC0, dst_hi, IA32_EDX));
1886 case BPF_JMP | BPF_CALL:
1888 const u8 *r1 = bpf2ia32[BPF_REG_1];
1889 const u8 *r2 = bpf2ia32[BPF_REG_2];
1890 const u8 *r3 = bpf2ia32[BPF_REG_3];
1891 const u8 *r4 = bpf2ia32[BPF_REG_4];
1892 const u8 *r5 = bpf2ia32[BPF_REG_5];
1894 if (insn->src_reg == BPF_PSEUDO_CALL)
1897 func = (u8 *) __bpf_call_base + imm32;
1898 jmp_offset = func - (image + addrs[i]);
1900 if (!imm32 || !is_simm32(jmp_offset)) {
1901 pr_err("unsupported BPF func %d addr %p image %p\n",
1902 imm32, func, image);
1906 /* mov eax,dword ptr [ebp+off] */
1907 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1909 /* mov edx,dword ptr [ebp+off] */
1910 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EDX),
1913 emit_push_r64(r5, &prog);
1914 emit_push_r64(r4, &prog);
1915 emit_push_r64(r3, &prog);
1916 emit_push_r64(r2, &prog);
1918 EMIT1_off32(0xE8, jmp_offset + 9);
1920 /* mov dword ptr [ebp+off],eax */
1921 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EAX),
1923 /* mov dword ptr [ebp+off],edx */
1924 EMIT3(0x89, add_2reg(0x40, IA32_EBP, IA32_EDX),
1928 EMIT3(0x83, add_1reg(0xC0, IA32_ESP), 32);
1931 case BPF_JMP | BPF_TAIL_CALL:
1932 emit_bpf_tail_call(&prog);
1936 case BPF_JMP | BPF_JEQ | BPF_X:
1937 case BPF_JMP | BPF_JNE | BPF_X:
1938 case BPF_JMP | BPF_JGT | BPF_X:
1939 case BPF_JMP | BPF_JLT | BPF_X:
1940 case BPF_JMP | BPF_JGE | BPF_X:
1941 case BPF_JMP | BPF_JLE | BPF_X:
1942 case BPF_JMP32 | BPF_JEQ | BPF_X:
1943 case BPF_JMP32 | BPF_JNE | BPF_X:
1944 case BPF_JMP32 | BPF_JGT | BPF_X:
1945 case BPF_JMP32 | BPF_JLT | BPF_X:
1946 case BPF_JMP32 | BPF_JGE | BPF_X:
1947 case BPF_JMP32 | BPF_JLE | BPF_X:
1948 case BPF_JMP32 | BPF_JSGT | BPF_X:
1949 case BPF_JMP32 | BPF_JSLE | BPF_X:
1950 case BPF_JMP32 | BPF_JSLT | BPF_X:
1951 case BPF_JMP32 | BPF_JSGE | BPF_X: {
1952 bool is_jmp64 = BPF_CLASS(insn->code) == BPF_JMP;
1953 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
1954 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
1955 u8 sreg_lo = sstk ? IA32_ECX : src_lo;
1956 u8 sreg_hi = sstk ? IA32_EBX : src_hi;
1959 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
1963 add_2reg(0x40, IA32_EBP,
1969 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
1973 add_2reg(0x40, IA32_EBP,
1979 /* cmp dreg_hi,sreg_hi */
1980 EMIT2(0x39, add_2reg(0xC0, dreg_hi, sreg_hi));
1983 /* cmp dreg_lo,sreg_lo */
1984 EMIT2(0x39, add_2reg(0xC0, dreg_lo, sreg_lo));
1987 case BPF_JMP | BPF_JSGT | BPF_X:
1988 case BPF_JMP | BPF_JSLE | BPF_X:
1989 case BPF_JMP | BPF_JSLT | BPF_X:
1990 case BPF_JMP | BPF_JSGE | BPF_X: {
1991 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
1992 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
1993 u8 sreg_lo = sstk ? IA32_ECX : src_lo;
1994 u8 sreg_hi = sstk ? IA32_EBX : src_hi;
1997 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
2000 add_2reg(0x40, IA32_EBP,
2006 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
2009 add_2reg(0x40, IA32_EBP,
2014 /* cmp dreg_hi,sreg_hi */
2015 EMIT2(0x39, add_2reg(0xC0, dreg_hi, sreg_hi));
2016 EMIT2(IA32_JNE, 10);
2017 /* cmp dreg_lo,sreg_lo */
2018 EMIT2(0x39, add_2reg(0xC0, dreg_lo, sreg_lo));
2019 goto emit_cond_jmp_signed;
2021 case BPF_JMP | BPF_JSET | BPF_X:
2022 case BPF_JMP32 | BPF_JSET | BPF_X: {
2023 bool is_jmp64 = BPF_CLASS(insn->code) == BPF_JMP;
2024 u8 dreg_lo = IA32_EAX;
2025 u8 dreg_hi = IA32_EDX;
2026 u8 sreg_lo = sstk ? IA32_ECX : src_lo;
2027 u8 sreg_hi = sstk ? IA32_EBX : src_hi;
2030 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
2034 add_2reg(0x40, IA32_EBP,
2038 /* mov dreg_lo,dst_lo */
2039 EMIT2(0x89, add_2reg(0xC0, dreg_lo, dst_lo));
2041 /* mov dreg_hi,dst_hi */
2043 add_2reg(0xC0, dreg_hi, dst_hi));
2047 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_ECX),
2051 add_2reg(0x40, IA32_EBP,
2055 /* and dreg_lo,sreg_lo */
2056 EMIT2(0x23, add_2reg(0xC0, sreg_lo, dreg_lo));
2058 /* and dreg_hi,sreg_hi */
2059 EMIT2(0x23, add_2reg(0xC0, sreg_hi, dreg_hi));
2060 /* or dreg_lo,dreg_hi */
2061 EMIT2(0x09, add_2reg(0xC0, dreg_lo, dreg_hi));
2065 case BPF_JMP | BPF_JSET | BPF_K:
2066 case BPF_JMP32 | BPF_JSET | BPF_K: {
2067 bool is_jmp64 = BPF_CLASS(insn->code) == BPF_JMP;
2068 u8 dreg_lo = IA32_EAX;
2069 u8 dreg_hi = IA32_EDX;
2070 u8 sreg_lo = IA32_ECX;
2071 u8 sreg_hi = IA32_EBX;
2075 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
2079 add_2reg(0x40, IA32_EBP,
2083 /* mov dreg_lo,dst_lo */
2084 EMIT2(0x89, add_2reg(0xC0, dreg_lo, dst_lo));
2086 /* mov dreg_hi,dst_hi */
2088 add_2reg(0xC0, dreg_hi, dst_hi));
2092 EMIT2_off32(0xC7, add_1reg(0xC0, sreg_lo), imm32);
2094 /* and dreg_lo,sreg_lo */
2095 EMIT2(0x23, add_2reg(0xC0, sreg_lo, dreg_lo));
2097 hi = imm32 & (1 << 31) ? (u32)~0 : 0;
2099 EMIT2_off32(0xC7, add_1reg(0xC0, sreg_hi), hi);
2100 /* and dreg_hi,sreg_hi */
2101 EMIT2(0x23, add_2reg(0xC0, sreg_hi, dreg_hi));
2102 /* or dreg_lo,dreg_hi */
2103 EMIT2(0x09, add_2reg(0xC0, dreg_lo, dreg_hi));
2107 case BPF_JMP | BPF_JEQ | BPF_K:
2108 case BPF_JMP | BPF_JNE | BPF_K:
2109 case BPF_JMP | BPF_JGT | BPF_K:
2110 case BPF_JMP | BPF_JLT | BPF_K:
2111 case BPF_JMP | BPF_JGE | BPF_K:
2112 case BPF_JMP | BPF_JLE | BPF_K:
2113 case BPF_JMP32 | BPF_JEQ | BPF_K:
2114 case BPF_JMP32 | BPF_JNE | BPF_K:
2115 case BPF_JMP32 | BPF_JGT | BPF_K:
2116 case BPF_JMP32 | BPF_JLT | BPF_K:
2117 case BPF_JMP32 | BPF_JGE | BPF_K:
2118 case BPF_JMP32 | BPF_JLE | BPF_K:
2119 case BPF_JMP32 | BPF_JSGT | BPF_K:
2120 case BPF_JMP32 | BPF_JSLE | BPF_K:
2121 case BPF_JMP32 | BPF_JSLT | BPF_K:
2122 case BPF_JMP32 | BPF_JSGE | BPF_K: {
2123 bool is_jmp64 = BPF_CLASS(insn->code) == BPF_JMP;
2124 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
2125 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
2126 u8 sreg_lo = IA32_ECX;
2127 u8 sreg_hi = IA32_EBX;
2131 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
2135 add_2reg(0x40, IA32_EBP,
2141 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), imm32);
2143 hi = imm32 & (1 << 31) ? (u32)~0 : 0;
2145 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EBX), hi);
2146 /* cmp dreg_hi,sreg_hi */
2147 EMIT2(0x39, add_2reg(0xC0, dreg_hi, sreg_hi));
2150 /* cmp dreg_lo,sreg_lo */
2151 EMIT2(0x39, add_2reg(0xC0, dreg_lo, sreg_lo));
2153 emit_cond_jmp: jmp_cond = get_cond_jmp_opcode(BPF_OP(code), false);
2154 if (jmp_cond == COND_JMP_OPCODE_INVALID)
2156 jmp_offset = addrs[i + insn->off] - addrs[i];
2157 if (is_imm8(jmp_offset)) {
2158 EMIT2(jmp_cond, jmp_offset);
2159 } else if (is_simm32(jmp_offset)) {
2160 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
2162 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
2167 case BPF_JMP | BPF_JSGT | BPF_K:
2168 case BPF_JMP | BPF_JSLE | BPF_K:
2169 case BPF_JMP | BPF_JSLT | BPF_K:
2170 case BPF_JMP | BPF_JSGE | BPF_K: {
2171 u8 dreg_lo = dstk ? IA32_EAX : dst_lo;
2172 u8 dreg_hi = dstk ? IA32_EDX : dst_hi;
2173 u8 sreg_lo = IA32_ECX;
2174 u8 sreg_hi = IA32_EBX;
2178 EMIT3(0x8B, add_2reg(0x40, IA32_EBP, IA32_EAX),
2181 add_2reg(0x40, IA32_EBP,
2187 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), imm32);
2188 hi = imm32 & (1 << 31) ? (u32)~0 : 0;
2190 EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EBX), hi);
2191 /* cmp dreg_hi,sreg_hi */
2192 EMIT2(0x39, add_2reg(0xC0, dreg_hi, sreg_hi));
2193 EMIT2(IA32_JNE, 10);
2194 /* cmp dreg_lo,sreg_lo */
2195 EMIT2(0x39, add_2reg(0xC0, dreg_lo, sreg_lo));
2198 * For simplicity of branch offset computation,
2199 * let's use fixed jump coding here.
2201 emit_cond_jmp_signed: /* Check the condition for low 32-bit comparison */
2202 jmp_cond = get_cond_jmp_opcode(BPF_OP(code), true);
2203 if (jmp_cond == COND_JMP_OPCODE_INVALID)
2205 jmp_offset = addrs[i + insn->off] - addrs[i] + 8;
2206 if (is_simm32(jmp_offset)) {
2207 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
2209 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
2214 /* Check the condition for high 32-bit comparison */
2215 jmp_cond = get_cond_jmp_opcode(BPF_OP(code), false);
2216 if (jmp_cond == COND_JMP_OPCODE_INVALID)
2218 jmp_offset = addrs[i + insn->off] - addrs[i];
2219 if (is_simm32(jmp_offset)) {
2220 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
2222 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
2227 case BPF_JMP | BPF_JA:
2228 if (insn->off == -1)
2229 /* -1 jmp instructions will always jump
2230 * backwards two bytes. Explicitly handling
2231 * this case avoids wasting too many passes
2232 * when there are long sequences of replaced
2237 jmp_offset = addrs[i + insn->off] - addrs[i];
2240 /* Optimize out nop jumps */
2243 if (is_imm8(jmp_offset)) {
2244 EMIT2(0xEB, jmp_offset);
2245 } else if (is_simm32(jmp_offset)) {
2246 EMIT1_off32(0xE9, jmp_offset);
2248 pr_err("jmp gen bug %llx\n", jmp_offset);
2252 /* STX XADD: lock *(u32 *)(dst + off) += src */
2253 case BPF_STX | BPF_XADD | BPF_W:
2254 /* STX XADD: lock *(u64 *)(dst + off) += src */
2255 case BPF_STX | BPF_XADD | BPF_DW:
2257 case BPF_JMP | BPF_EXIT:
2259 jmp_offset = ctx->cleanup_addr - addrs[i];
2263 /* Update cleanup_addr */
2264 ctx->cleanup_addr = proglen;
2265 emit_epilogue(&prog, bpf_prog->aux->stack_depth);
2268 pr_info_once("*** NOT YET: opcode %02x ***\n", code);
2272 * This error will be seen if new instruction was added
2273 * to interpreter, but not to JIT or if there is junk in
2276 pr_err("bpf_jit: unknown opcode %02x\n", code);
2281 if (ilen > BPF_MAX_INSN_SIZE) {
2282 pr_err("bpf_jit: fatal insn size error\n");
2288 * When populating the image, assert that:
2290 * i) We do not write beyond the allocated space, and
2291 * ii) addrs[i] did not change from the prior run, in order
2292 * to validate assumptions made for computing branch
2295 if (unlikely(proglen + ilen > oldproglen ||
2296 proglen + ilen != addrs[i])) {
2297 pr_err("bpf_jit: fatal error\n");
2300 memcpy(image + proglen, temp, ilen);
2309 bool bpf_jit_needs_zext(void)
2314 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
2316 struct bpf_binary_header *header = NULL;
2317 struct bpf_prog *tmp, *orig_prog = prog;
2318 int proglen, oldproglen = 0;
2319 struct jit_context ctx = {};
2320 bool tmp_blinded = false;
2326 if (!prog->jit_requested)
2329 tmp = bpf_jit_blind_constants(prog);
2331 * If blinding was requested and we failed during blinding,
2332 * we must fall back to the interpreter.
2341 addrs = kmalloc_array(prog->len, sizeof(*addrs), GFP_KERNEL);
2348 * Before first pass, make a rough estimation of addrs[]
2349 * each BPF instruction is translated to less than 64 bytes
2351 for (proglen = 0, i = 0; i < prog->len; i++) {
2355 ctx.cleanup_addr = proglen;
2358 * JITed image shrinks with every pass and the loop iterates
2359 * until the image stops shrinking. Very large BPF programs
2360 * may converge on the last pass. In such case do one more
2361 * pass to emit the final image.
2363 for (pass = 0; pass < 20 || image; pass++) {
2364 proglen = do_jit(prog, addrs, image, oldproglen, &ctx);
2369 bpf_jit_binary_free(header);
2374 if (proglen != oldproglen) {
2375 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n",
2376 proglen, oldproglen);
2381 if (proglen == oldproglen) {
2382 header = bpf_jit_binary_alloc(proglen, &image,
2389 oldproglen = proglen;
2393 if (bpf_jit_enable > 1)
2394 bpf_jit_dump(prog->len, proglen, pass + 1, image);
2397 bpf_jit_binary_lock_ro(header);
2398 prog->bpf_func = (void *)image;
2400 prog->jited_len = proglen;
2409 bpf_jit_prog_release_other(prog, prog == orig_prog ?