1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Common functionality for RV32 and RV64 BPF JIT compilers
5 * Copyright (c) 2019 Björn Töpel <bjorn.topel@gmail.com>
12 #include <linux/bpf.h>
13 #include <linux/filter.h>
14 #include <asm/cacheflush.h>
16 static inline bool rvc_enabled(void)
18 return IS_ENABLED(CONFIG_RISCV_ISA_C);
22 RV_REG_ZERO = 0, /* The constant value 0 */
23 RV_REG_RA = 1, /* Return address */
24 RV_REG_SP = 2, /* Stack pointer */
25 RV_REG_GP = 3, /* Global pointer */
26 RV_REG_TP = 4, /* Thread pointer */
27 RV_REG_T0 = 5, /* Temporaries */
30 RV_REG_FP = 8, /* Saved register/frame pointer */
31 RV_REG_S1 = 9, /* Saved register */
32 RV_REG_A0 = 10, /* Function argument/return values */
33 RV_REG_A1 = 11, /* Function arguments */
40 RV_REG_S2 = 18, /* Saved registers */
50 RV_REG_T3 = 28, /* Temporaries */
56 static inline bool is_creg(u8 reg)
58 return (1 << reg) & (BIT(RV_REG_FP) |
68 struct rv_jit_context {
69 struct bpf_prog *prog;
70 u16 *insns; /* RV insns */
73 int *offset; /* BPF to RV */
79 /* Convert from ninsns to bytes. */
80 static inline int ninsns_rvoff(int ninsns)
86 struct bpf_binary_header *header;
88 struct rv_jit_context ctx;
91 static inline void bpf_fill_ill_insns(void *area, unsigned int size)
93 memset(area, 0, size);
96 static inline void bpf_flush_icache(void *start, void *end)
98 flush_icache_range((unsigned long)start, (unsigned long)end);
101 /* Emit a 4-byte riscv instruction. */
102 static inline void emit(const u32 insn, struct rv_jit_context *ctx)
105 ctx->insns[ctx->ninsns] = insn;
106 ctx->insns[ctx->ninsns + 1] = (insn >> 16);
112 /* Emit a 2-byte riscv compressed instruction. */
113 static inline void emitc(const u16 insn, struct rv_jit_context *ctx)
115 BUILD_BUG_ON(!rvc_enabled());
118 ctx->insns[ctx->ninsns] = insn;
123 static inline int epilogue_offset(struct rv_jit_context *ctx)
125 int to = ctx->epilogue_offset, from = ctx->ninsns;
127 return ninsns_rvoff(to - from);
130 /* Return -1 or inverted cond. */
131 static inline int invert_bpf_cond(u8 cond)
158 static inline bool is_6b_int(long val)
160 return -(1L << 5) <= val && val < (1L << 5);
163 static inline bool is_7b_uint(unsigned long val)
165 return val < (1UL << 7);
168 static inline bool is_8b_uint(unsigned long val)
170 return val < (1UL << 8);
173 static inline bool is_9b_uint(unsigned long val)
175 return val < (1UL << 9);
178 static inline bool is_10b_int(long val)
180 return -(1L << 9) <= val && val < (1L << 9);
183 static inline bool is_10b_uint(unsigned long val)
185 return val < (1UL << 10);
188 static inline bool is_12b_int(long val)
190 return -(1L << 11) <= val && val < (1L << 11);
193 static inline int is_12b_check(int off, int insn)
195 if (!is_12b_int(off)) {
196 pr_err("bpf-jit: insn=%d 12b < offset=%d not supported yet!\n",
203 static inline bool is_13b_int(long val)
205 return -(1L << 12) <= val && val < (1L << 12);
208 static inline bool is_21b_int(long val)
210 return -(1L << 20) <= val && val < (1L << 20);
213 static inline int rv_offset(int insn, int off, struct rv_jit_context *ctx)
217 off++; /* BPF branch is from PC+1, RV is from PC */
218 from = (insn > 0) ? ctx->offset[insn - 1] : 0;
219 to = (insn + off > 0) ? ctx->offset[insn + off - 1] : 0;
220 return ninsns_rvoff(to - from);
223 /* Instruction formats. */
225 static inline u32 rv_r_insn(u8 funct7, u8 rs2, u8 rs1, u8 funct3, u8 rd,
228 return (funct7 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) |
232 static inline u32 rv_i_insn(u16 imm11_0, u8 rs1, u8 funct3, u8 rd, u8 opcode)
234 return (imm11_0 << 20) | (rs1 << 15) | (funct3 << 12) | (rd << 7) |
238 static inline u32 rv_s_insn(u16 imm11_0, u8 rs2, u8 rs1, u8 funct3, u8 opcode)
240 u8 imm11_5 = imm11_0 >> 5, imm4_0 = imm11_0 & 0x1f;
242 return (imm11_5 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) |
243 (imm4_0 << 7) | opcode;
246 static inline u32 rv_b_insn(u16 imm12_1, u8 rs2, u8 rs1, u8 funct3, u8 opcode)
248 u8 imm12 = ((imm12_1 & 0x800) >> 5) | ((imm12_1 & 0x3f0) >> 4);
249 u8 imm4_1 = ((imm12_1 & 0xf) << 1) | ((imm12_1 & 0x400) >> 10);
251 return (imm12 << 25) | (rs2 << 20) | (rs1 << 15) | (funct3 << 12) |
252 (imm4_1 << 7) | opcode;
255 static inline u32 rv_u_insn(u32 imm31_12, u8 rd, u8 opcode)
257 return (imm31_12 << 12) | (rd << 7) | opcode;
260 static inline u32 rv_j_insn(u32 imm20_1, u8 rd, u8 opcode)
264 imm = (imm20_1 & 0x80000) | ((imm20_1 & 0x3ff) << 9) |
265 ((imm20_1 & 0x400) >> 2) | ((imm20_1 & 0x7f800) >> 11);
267 return (imm << 12) | (rd << 7) | opcode;
270 static inline u32 rv_amo_insn(u8 funct5, u8 aq, u8 rl, u8 rs2, u8 rs1,
271 u8 funct3, u8 rd, u8 opcode)
273 u8 funct7 = (funct5 << 2) | (aq << 1) | rl;
275 return rv_r_insn(funct7, rs2, rs1, funct3, rd, opcode);
278 /* RISC-V compressed instruction formats. */
280 static inline u16 rv_cr_insn(u8 funct4, u8 rd, u8 rs2, u8 op)
282 return (funct4 << 12) | (rd << 7) | (rs2 << 2) | op;
285 static inline u16 rv_ci_insn(u8 funct3, u32 imm6, u8 rd, u8 op)
289 imm = ((imm6 & 0x20) << 7) | ((imm6 & 0x1f) << 2);
290 return (funct3 << 13) | (rd << 7) | op | imm;
293 static inline u16 rv_css_insn(u8 funct3, u32 uimm, u8 rs2, u8 op)
295 return (funct3 << 13) | (uimm << 7) | (rs2 << 2) | op;
298 static inline u16 rv_ciw_insn(u8 funct3, u32 uimm, u8 rd, u8 op)
300 return (funct3 << 13) | (uimm << 5) | ((rd & 0x7) << 2) | op;
303 static inline u16 rv_cl_insn(u8 funct3, u32 imm_hi, u8 rs1, u32 imm_lo, u8 rd,
306 return (funct3 << 13) | (imm_hi << 10) | ((rs1 & 0x7) << 7) |
307 (imm_lo << 5) | ((rd & 0x7) << 2) | op;
310 static inline u16 rv_cs_insn(u8 funct3, u32 imm_hi, u8 rs1, u32 imm_lo, u8 rs2,
313 return (funct3 << 13) | (imm_hi << 10) | ((rs1 & 0x7) << 7) |
314 (imm_lo << 5) | ((rs2 & 0x7) << 2) | op;
317 static inline u16 rv_ca_insn(u8 funct6, u8 rd, u8 funct2, u8 rs2, u8 op)
319 return (funct6 << 10) | ((rd & 0x7) << 7) | (funct2 << 5) |
320 ((rs2 & 0x7) << 2) | op;
323 static inline u16 rv_cb_insn(u8 funct3, u32 imm6, u8 funct2, u8 rd, u8 op)
327 imm = ((imm6 & 0x20) << 7) | ((imm6 & 0x1f) << 2);
328 return (funct3 << 13) | (funct2 << 10) | ((rd & 0x7) << 7) | op | imm;
331 /* Instructions shared by both RV32 and RV64. */
333 static inline u32 rv_addi(u8 rd, u8 rs1, u16 imm11_0)
335 return rv_i_insn(imm11_0, rs1, 0, rd, 0x13);
338 static inline u32 rv_andi(u8 rd, u8 rs1, u16 imm11_0)
340 return rv_i_insn(imm11_0, rs1, 7, rd, 0x13);
343 static inline u32 rv_ori(u8 rd, u8 rs1, u16 imm11_0)
345 return rv_i_insn(imm11_0, rs1, 6, rd, 0x13);
348 static inline u32 rv_xori(u8 rd, u8 rs1, u16 imm11_0)
350 return rv_i_insn(imm11_0, rs1, 4, rd, 0x13);
353 static inline u32 rv_slli(u8 rd, u8 rs1, u16 imm11_0)
355 return rv_i_insn(imm11_0, rs1, 1, rd, 0x13);
358 static inline u32 rv_srli(u8 rd, u8 rs1, u16 imm11_0)
360 return rv_i_insn(imm11_0, rs1, 5, rd, 0x13);
363 static inline u32 rv_srai(u8 rd, u8 rs1, u16 imm11_0)
365 return rv_i_insn(0x400 | imm11_0, rs1, 5, rd, 0x13);
368 static inline u32 rv_lui(u8 rd, u32 imm31_12)
370 return rv_u_insn(imm31_12, rd, 0x37);
373 static inline u32 rv_auipc(u8 rd, u32 imm31_12)
375 return rv_u_insn(imm31_12, rd, 0x17);
378 static inline u32 rv_add(u8 rd, u8 rs1, u8 rs2)
380 return rv_r_insn(0, rs2, rs1, 0, rd, 0x33);
383 static inline u32 rv_sub(u8 rd, u8 rs1, u8 rs2)
385 return rv_r_insn(0x20, rs2, rs1, 0, rd, 0x33);
388 static inline u32 rv_sltu(u8 rd, u8 rs1, u8 rs2)
390 return rv_r_insn(0, rs2, rs1, 3, rd, 0x33);
393 static inline u32 rv_and(u8 rd, u8 rs1, u8 rs2)
395 return rv_r_insn(0, rs2, rs1, 7, rd, 0x33);
398 static inline u32 rv_or(u8 rd, u8 rs1, u8 rs2)
400 return rv_r_insn(0, rs2, rs1, 6, rd, 0x33);
403 static inline u32 rv_xor(u8 rd, u8 rs1, u8 rs2)
405 return rv_r_insn(0, rs2, rs1, 4, rd, 0x33);
408 static inline u32 rv_sll(u8 rd, u8 rs1, u8 rs2)
410 return rv_r_insn(0, rs2, rs1, 1, rd, 0x33);
413 static inline u32 rv_srl(u8 rd, u8 rs1, u8 rs2)
415 return rv_r_insn(0, rs2, rs1, 5, rd, 0x33);
418 static inline u32 rv_sra(u8 rd, u8 rs1, u8 rs2)
420 return rv_r_insn(0x20, rs2, rs1, 5, rd, 0x33);
423 static inline u32 rv_mul(u8 rd, u8 rs1, u8 rs2)
425 return rv_r_insn(1, rs2, rs1, 0, rd, 0x33);
428 static inline u32 rv_mulhu(u8 rd, u8 rs1, u8 rs2)
430 return rv_r_insn(1, rs2, rs1, 3, rd, 0x33);
433 static inline u32 rv_divu(u8 rd, u8 rs1, u8 rs2)
435 return rv_r_insn(1, rs2, rs1, 5, rd, 0x33);
438 static inline u32 rv_remu(u8 rd, u8 rs1, u8 rs2)
440 return rv_r_insn(1, rs2, rs1, 7, rd, 0x33);
443 static inline u32 rv_jal(u8 rd, u32 imm20_1)
445 return rv_j_insn(imm20_1, rd, 0x6f);
448 static inline u32 rv_jalr(u8 rd, u8 rs1, u16 imm11_0)
450 return rv_i_insn(imm11_0, rs1, 0, rd, 0x67);
453 static inline u32 rv_beq(u8 rs1, u8 rs2, u16 imm12_1)
455 return rv_b_insn(imm12_1, rs2, rs1, 0, 0x63);
458 static inline u32 rv_bne(u8 rs1, u8 rs2, u16 imm12_1)
460 return rv_b_insn(imm12_1, rs2, rs1, 1, 0x63);
463 static inline u32 rv_bltu(u8 rs1, u8 rs2, u16 imm12_1)
465 return rv_b_insn(imm12_1, rs2, rs1, 6, 0x63);
468 static inline u32 rv_bgtu(u8 rs1, u8 rs2, u16 imm12_1)
470 return rv_bltu(rs2, rs1, imm12_1);
473 static inline u32 rv_bgeu(u8 rs1, u8 rs2, u16 imm12_1)
475 return rv_b_insn(imm12_1, rs2, rs1, 7, 0x63);
478 static inline u32 rv_bleu(u8 rs1, u8 rs2, u16 imm12_1)
480 return rv_bgeu(rs2, rs1, imm12_1);
483 static inline u32 rv_blt(u8 rs1, u8 rs2, u16 imm12_1)
485 return rv_b_insn(imm12_1, rs2, rs1, 4, 0x63);
488 static inline u32 rv_bgt(u8 rs1, u8 rs2, u16 imm12_1)
490 return rv_blt(rs2, rs1, imm12_1);
493 static inline u32 rv_bge(u8 rs1, u8 rs2, u16 imm12_1)
495 return rv_b_insn(imm12_1, rs2, rs1, 5, 0x63);
498 static inline u32 rv_ble(u8 rs1, u8 rs2, u16 imm12_1)
500 return rv_bge(rs2, rs1, imm12_1);
503 static inline u32 rv_lw(u8 rd, u16 imm11_0, u8 rs1)
505 return rv_i_insn(imm11_0, rs1, 2, rd, 0x03);
508 static inline u32 rv_lbu(u8 rd, u16 imm11_0, u8 rs1)
510 return rv_i_insn(imm11_0, rs1, 4, rd, 0x03);
513 static inline u32 rv_lhu(u8 rd, u16 imm11_0, u8 rs1)
515 return rv_i_insn(imm11_0, rs1, 5, rd, 0x03);
518 static inline u32 rv_sb(u8 rs1, u16 imm11_0, u8 rs2)
520 return rv_s_insn(imm11_0, rs2, rs1, 0, 0x23);
523 static inline u32 rv_sh(u8 rs1, u16 imm11_0, u8 rs2)
525 return rv_s_insn(imm11_0, rs2, rs1, 1, 0x23);
528 static inline u32 rv_sw(u8 rs1, u16 imm11_0, u8 rs2)
530 return rv_s_insn(imm11_0, rs2, rs1, 2, 0x23);
533 static inline u32 rv_amoadd_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
535 return rv_amo_insn(0, aq, rl, rs2, rs1, 2, rd, 0x2f);
538 static inline u32 rv_amoand_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
540 return rv_amo_insn(0xc, aq, rl, rs2, rs1, 2, rd, 0x2f);
543 static inline u32 rv_amoor_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
545 return rv_amo_insn(0x8, aq, rl, rs2, rs1, 2, rd, 0x2f);
548 static inline u32 rv_amoxor_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
550 return rv_amo_insn(0x4, aq, rl, rs2, rs1, 2, rd, 0x2f);
553 static inline u32 rv_amoswap_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
555 return rv_amo_insn(0x1, aq, rl, rs2, rs1, 2, rd, 0x2f);
558 static inline u32 rv_lr_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
560 return rv_amo_insn(0x2, aq, rl, rs2, rs1, 2, rd, 0x2f);
563 static inline u32 rv_sc_w(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
565 return rv_amo_insn(0x3, aq, rl, rs2, rs1, 2, rd, 0x2f);
568 static inline u32 rv_fence(u8 pred, u8 succ)
570 u16 imm11_0 = pred << 4 | succ;
572 return rv_i_insn(imm11_0, 0, 0, 0, 0xf);
575 /* RVC instrutions. */
577 static inline u16 rvc_addi4spn(u8 rd, u32 imm10)
581 imm = ((imm10 & 0x30) << 2) | ((imm10 & 0x3c0) >> 4) |
582 ((imm10 & 0x4) >> 1) | ((imm10 & 0x8) >> 3);
583 return rv_ciw_insn(0x0, imm, rd, 0x0);
586 static inline u16 rvc_lw(u8 rd, u32 imm7, u8 rs1)
590 imm_hi = (imm7 & 0x38) >> 3;
591 imm_lo = ((imm7 & 0x4) >> 1) | ((imm7 & 0x40) >> 6);
592 return rv_cl_insn(0x2, imm_hi, rs1, imm_lo, rd, 0x0);
595 static inline u16 rvc_sw(u8 rs1, u32 imm7, u8 rs2)
599 imm_hi = (imm7 & 0x38) >> 3;
600 imm_lo = ((imm7 & 0x4) >> 1) | ((imm7 & 0x40) >> 6);
601 return rv_cs_insn(0x6, imm_hi, rs1, imm_lo, rs2, 0x0);
604 static inline u16 rvc_addi(u8 rd, u32 imm6)
606 return rv_ci_insn(0, imm6, rd, 0x1);
609 static inline u16 rvc_li(u8 rd, u32 imm6)
611 return rv_ci_insn(0x2, imm6, rd, 0x1);
614 static inline u16 rvc_addi16sp(u32 imm10)
618 imm = ((imm10 & 0x200) >> 4) | (imm10 & 0x10) | ((imm10 & 0x40) >> 3) |
619 ((imm10 & 0x180) >> 6) | ((imm10 & 0x20) >> 5);
620 return rv_ci_insn(0x3, imm, RV_REG_SP, 0x1);
623 static inline u16 rvc_lui(u8 rd, u32 imm6)
625 return rv_ci_insn(0x3, imm6, rd, 0x1);
628 static inline u16 rvc_srli(u8 rd, u32 imm6)
630 return rv_cb_insn(0x4, imm6, 0, rd, 0x1);
633 static inline u16 rvc_srai(u8 rd, u32 imm6)
635 return rv_cb_insn(0x4, imm6, 0x1, rd, 0x1);
638 static inline u16 rvc_andi(u8 rd, u32 imm6)
640 return rv_cb_insn(0x4, imm6, 0x2, rd, 0x1);
643 static inline u16 rvc_sub(u8 rd, u8 rs)
645 return rv_ca_insn(0x23, rd, 0, rs, 0x1);
648 static inline u16 rvc_xor(u8 rd, u8 rs)
650 return rv_ca_insn(0x23, rd, 0x1, rs, 0x1);
653 static inline u16 rvc_or(u8 rd, u8 rs)
655 return rv_ca_insn(0x23, rd, 0x2, rs, 0x1);
658 static inline u16 rvc_and(u8 rd, u8 rs)
660 return rv_ca_insn(0x23, rd, 0x3, rs, 0x1);
663 static inline u16 rvc_slli(u8 rd, u32 imm6)
665 return rv_ci_insn(0, imm6, rd, 0x2);
668 static inline u16 rvc_lwsp(u8 rd, u32 imm8)
672 imm = ((imm8 & 0xc0) >> 6) | (imm8 & 0x3c);
673 return rv_ci_insn(0x2, imm, rd, 0x2);
676 static inline u16 rvc_jr(u8 rs1)
678 return rv_cr_insn(0x8, rs1, RV_REG_ZERO, 0x2);
681 static inline u16 rvc_mv(u8 rd, u8 rs)
683 return rv_cr_insn(0x8, rd, rs, 0x2);
686 static inline u16 rvc_jalr(u8 rs1)
688 return rv_cr_insn(0x9, rs1, RV_REG_ZERO, 0x2);
691 static inline u16 rvc_add(u8 rd, u8 rs)
693 return rv_cr_insn(0x9, rd, rs, 0x2);
696 static inline u16 rvc_swsp(u32 imm8, u8 rs2)
700 imm = (imm8 & 0x3c) | ((imm8 & 0xc0) >> 6);
701 return rv_css_insn(0x6, imm, rs2, 0x2);
705 * RV64-only instructions.
707 * These instructions are not available on RV32. Wrap them below a #if to
708 * ensure that the RV32 JIT doesn't emit any of these instructions.
711 #if __riscv_xlen == 64
713 static inline u32 rv_addiw(u8 rd, u8 rs1, u16 imm11_0)
715 return rv_i_insn(imm11_0, rs1, 0, rd, 0x1b);
718 static inline u32 rv_slliw(u8 rd, u8 rs1, u16 imm11_0)
720 return rv_i_insn(imm11_0, rs1, 1, rd, 0x1b);
723 static inline u32 rv_srliw(u8 rd, u8 rs1, u16 imm11_0)
725 return rv_i_insn(imm11_0, rs1, 5, rd, 0x1b);
728 static inline u32 rv_sraiw(u8 rd, u8 rs1, u16 imm11_0)
730 return rv_i_insn(0x400 | imm11_0, rs1, 5, rd, 0x1b);
733 static inline u32 rv_addw(u8 rd, u8 rs1, u8 rs2)
735 return rv_r_insn(0, rs2, rs1, 0, rd, 0x3b);
738 static inline u32 rv_subw(u8 rd, u8 rs1, u8 rs2)
740 return rv_r_insn(0x20, rs2, rs1, 0, rd, 0x3b);
743 static inline u32 rv_sllw(u8 rd, u8 rs1, u8 rs2)
745 return rv_r_insn(0, rs2, rs1, 1, rd, 0x3b);
748 static inline u32 rv_srlw(u8 rd, u8 rs1, u8 rs2)
750 return rv_r_insn(0, rs2, rs1, 5, rd, 0x3b);
753 static inline u32 rv_sraw(u8 rd, u8 rs1, u8 rs2)
755 return rv_r_insn(0x20, rs2, rs1, 5, rd, 0x3b);
758 static inline u32 rv_mulw(u8 rd, u8 rs1, u8 rs2)
760 return rv_r_insn(1, rs2, rs1, 0, rd, 0x3b);
763 static inline u32 rv_divuw(u8 rd, u8 rs1, u8 rs2)
765 return rv_r_insn(1, rs2, rs1, 5, rd, 0x3b);
768 static inline u32 rv_remuw(u8 rd, u8 rs1, u8 rs2)
770 return rv_r_insn(1, rs2, rs1, 7, rd, 0x3b);
773 static inline u32 rv_ld(u8 rd, u16 imm11_0, u8 rs1)
775 return rv_i_insn(imm11_0, rs1, 3, rd, 0x03);
778 static inline u32 rv_lwu(u8 rd, u16 imm11_0, u8 rs1)
780 return rv_i_insn(imm11_0, rs1, 6, rd, 0x03);
783 static inline u32 rv_sd(u8 rs1, u16 imm11_0, u8 rs2)
785 return rv_s_insn(imm11_0, rs2, rs1, 3, 0x23);
788 static inline u32 rv_amoadd_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
790 return rv_amo_insn(0, aq, rl, rs2, rs1, 3, rd, 0x2f);
793 static inline u32 rv_amoand_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
795 return rv_amo_insn(0xc, aq, rl, rs2, rs1, 3, rd, 0x2f);
798 static inline u32 rv_amoor_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
800 return rv_amo_insn(0x8, aq, rl, rs2, rs1, 3, rd, 0x2f);
803 static inline u32 rv_amoxor_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
805 return rv_amo_insn(0x4, aq, rl, rs2, rs1, 3, rd, 0x2f);
808 static inline u32 rv_amoswap_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
810 return rv_amo_insn(0x1, aq, rl, rs2, rs1, 3, rd, 0x2f);
813 static inline u32 rv_lr_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
815 return rv_amo_insn(0x2, aq, rl, rs2, rs1, 3, rd, 0x2f);
818 static inline u32 rv_sc_d(u8 rd, u8 rs2, u8 rs1, u8 aq, u8 rl)
820 return rv_amo_insn(0x3, aq, rl, rs2, rs1, 3, rd, 0x2f);
823 /* RV64-only RVC instructions. */
825 static inline u16 rvc_ld(u8 rd, u32 imm8, u8 rs1)
829 imm_hi = (imm8 & 0x38) >> 3;
830 imm_lo = (imm8 & 0xc0) >> 6;
831 return rv_cl_insn(0x3, imm_hi, rs1, imm_lo, rd, 0x0);
834 static inline u16 rvc_sd(u8 rs1, u32 imm8, u8 rs2)
838 imm_hi = (imm8 & 0x38) >> 3;
839 imm_lo = (imm8 & 0xc0) >> 6;
840 return rv_cs_insn(0x7, imm_hi, rs1, imm_lo, rs2, 0x0);
843 static inline u16 rvc_subw(u8 rd, u8 rs)
845 return rv_ca_insn(0x27, rd, 0, rs, 0x1);
848 static inline u16 rvc_addiw(u8 rd, u32 imm6)
850 return rv_ci_insn(0x1, imm6, rd, 0x1);
853 static inline u16 rvc_ldsp(u8 rd, u32 imm9)
857 imm = ((imm9 & 0x1c0) >> 6) | (imm9 & 0x38);
858 return rv_ci_insn(0x3, imm, rd, 0x2);
861 static inline u16 rvc_sdsp(u32 imm9, u8 rs2)
865 imm = (imm9 & 0x38) | ((imm9 & 0x1c0) >> 6);
866 return rv_css_insn(0x7, imm, rs2, 0x2);
869 #endif /* __riscv_xlen == 64 */
871 /* Helper functions that emit RVC instructions when possible. */
873 static inline void emit_jalr(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
875 if (rvc_enabled() && rd == RV_REG_RA && rs && !imm)
876 emitc(rvc_jalr(rs), ctx);
877 else if (rvc_enabled() && !rd && rs && !imm)
878 emitc(rvc_jr(rs), ctx);
880 emit(rv_jalr(rd, rs, imm), ctx);
883 static inline void emit_mv(u8 rd, u8 rs, struct rv_jit_context *ctx)
885 if (rvc_enabled() && rd && rs)
886 emitc(rvc_mv(rd, rs), ctx);
888 emit(rv_addi(rd, rs, 0), ctx);
891 static inline void emit_add(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
893 if (rvc_enabled() && rd && rd == rs1 && rs2)
894 emitc(rvc_add(rd, rs2), ctx);
896 emit(rv_add(rd, rs1, rs2), ctx);
899 static inline void emit_addi(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
901 if (rvc_enabled() && rd == RV_REG_SP && rd == rs && is_10b_int(imm) && imm && !(imm & 0xf))
902 emitc(rvc_addi16sp(imm), ctx);
903 else if (rvc_enabled() && is_creg(rd) && rs == RV_REG_SP && is_10b_uint(imm) &&
905 emitc(rvc_addi4spn(rd, imm), ctx);
906 else if (rvc_enabled() && rd && rd == rs && imm && is_6b_int(imm))
907 emitc(rvc_addi(rd, imm), ctx);
909 emit(rv_addi(rd, rs, imm), ctx);
912 static inline void emit_li(u8 rd, s32 imm, struct rv_jit_context *ctx)
914 if (rvc_enabled() && rd && is_6b_int(imm))
915 emitc(rvc_li(rd, imm), ctx);
917 emit(rv_addi(rd, RV_REG_ZERO, imm), ctx);
920 static inline void emit_lui(u8 rd, s32 imm, struct rv_jit_context *ctx)
922 if (rvc_enabled() && rd && rd != RV_REG_SP && is_6b_int(imm) && imm)
923 emitc(rvc_lui(rd, imm), ctx);
925 emit(rv_lui(rd, imm), ctx);
928 static inline void emit_slli(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
930 if (rvc_enabled() && rd && rd == rs && imm && (u32)imm < __riscv_xlen)
931 emitc(rvc_slli(rd, imm), ctx);
933 emit(rv_slli(rd, rs, imm), ctx);
936 static inline void emit_andi(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
938 if (rvc_enabled() && is_creg(rd) && rd == rs && is_6b_int(imm))
939 emitc(rvc_andi(rd, imm), ctx);
941 emit(rv_andi(rd, rs, imm), ctx);
944 static inline void emit_srli(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
946 if (rvc_enabled() && is_creg(rd) && rd == rs && imm && (u32)imm < __riscv_xlen)
947 emitc(rvc_srli(rd, imm), ctx);
949 emit(rv_srli(rd, rs, imm), ctx);
952 static inline void emit_srai(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
954 if (rvc_enabled() && is_creg(rd) && rd == rs && imm && (u32)imm < __riscv_xlen)
955 emitc(rvc_srai(rd, imm), ctx);
957 emit(rv_srai(rd, rs, imm), ctx);
960 static inline void emit_sub(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
962 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2))
963 emitc(rvc_sub(rd, rs2), ctx);
965 emit(rv_sub(rd, rs1, rs2), ctx);
968 static inline void emit_or(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
970 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2))
971 emitc(rvc_or(rd, rs2), ctx);
973 emit(rv_or(rd, rs1, rs2), ctx);
976 static inline void emit_and(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
978 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2))
979 emitc(rvc_and(rd, rs2), ctx);
981 emit(rv_and(rd, rs1, rs2), ctx);
984 static inline void emit_xor(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
986 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2))
987 emitc(rvc_xor(rd, rs2), ctx);
989 emit(rv_xor(rd, rs1, rs2), ctx);
992 static inline void emit_lw(u8 rd, s32 off, u8 rs1, struct rv_jit_context *ctx)
994 if (rvc_enabled() && rs1 == RV_REG_SP && rd && is_8b_uint(off) && !(off & 0x3))
995 emitc(rvc_lwsp(rd, off), ctx);
996 else if (rvc_enabled() && is_creg(rd) && is_creg(rs1) && is_7b_uint(off) && !(off & 0x3))
997 emitc(rvc_lw(rd, off, rs1), ctx);
999 emit(rv_lw(rd, off, rs1), ctx);
1002 static inline void emit_sw(u8 rs1, s32 off, u8 rs2, struct rv_jit_context *ctx)
1004 if (rvc_enabled() && rs1 == RV_REG_SP && is_8b_uint(off) && !(off & 0x3))
1005 emitc(rvc_swsp(off, rs2), ctx);
1006 else if (rvc_enabled() && is_creg(rs1) && is_creg(rs2) && is_7b_uint(off) && !(off & 0x3))
1007 emitc(rvc_sw(rs1, off, rs2), ctx);
1009 emit(rv_sw(rs1, off, rs2), ctx);
1012 /* RV64-only helper functions. */
1013 #if __riscv_xlen == 64
1015 static inline void emit_addiw(u8 rd, u8 rs, s32 imm, struct rv_jit_context *ctx)
1017 if (rvc_enabled() && rd && rd == rs && is_6b_int(imm))
1018 emitc(rvc_addiw(rd, imm), ctx);
1020 emit(rv_addiw(rd, rs, imm), ctx);
1023 static inline void emit_ld(u8 rd, s32 off, u8 rs1, struct rv_jit_context *ctx)
1025 if (rvc_enabled() && rs1 == RV_REG_SP && rd && is_9b_uint(off) && !(off & 0x7))
1026 emitc(rvc_ldsp(rd, off), ctx);
1027 else if (rvc_enabled() && is_creg(rd) && is_creg(rs1) && is_8b_uint(off) && !(off & 0x7))
1028 emitc(rvc_ld(rd, off, rs1), ctx);
1030 emit(rv_ld(rd, off, rs1), ctx);
1033 static inline void emit_sd(u8 rs1, s32 off, u8 rs2, struct rv_jit_context *ctx)
1035 if (rvc_enabled() && rs1 == RV_REG_SP && is_9b_uint(off) && !(off & 0x7))
1036 emitc(rvc_sdsp(off, rs2), ctx);
1037 else if (rvc_enabled() && is_creg(rs1) && is_creg(rs2) && is_8b_uint(off) && !(off & 0x7))
1038 emitc(rvc_sd(rs1, off, rs2), ctx);
1040 emit(rv_sd(rs1, off, rs2), ctx);
1043 static inline void emit_subw(u8 rd, u8 rs1, u8 rs2, struct rv_jit_context *ctx)
1045 if (rvc_enabled() && is_creg(rd) && rd == rs1 && is_creg(rs2))
1046 emitc(rvc_subw(rd, rs2), ctx);
1048 emit(rv_subw(rd, rs1, rs2), ctx);
1051 #endif /* __riscv_xlen == 64 */
1053 void bpf_jit_build_prologue(struct rv_jit_context *ctx);
1054 void bpf_jit_build_epilogue(struct rv_jit_context *ctx);
1056 int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
1059 #endif /* _BPF_JIT_H */