1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TQM 8560 Device Tree Source
5 * Copyright 2008 Freescale Semiconductor Inc.
6 * Copyright 2008 Wolfgang Grandegger <wg@grandegger.com>
11 /include/ "fsl/e500v1_power_isa.dtsi"
14 model = "tqc,tqm8560";
15 compatible = "tqc,tqm8560";
35 d-cache-line-size = <32>;
36 i-cache-line-size = <32>;
37 d-cache-size = <32768>;
38 i-cache-size = <32768>;
39 timebase-frequency = <0>;
41 clock-frequency = <0>;
42 next-level-cache = <&L2>;
47 device_type = "memory";
48 reg = <0x00000000 0x10000000>;
55 ranges = <0x0 0xe0000000 0x100000>;
57 compatible = "fsl,mpc8560-immr", "simple-bus";
60 compatible = "fsl,ecm-law";
66 compatible = "fsl,mpc8560-ecm", "fsl,ecm";
67 reg = <0x1000 0x1000>;
69 interrupt-parent = <&mpic>;
72 memory-controller@2000 {
73 compatible = "fsl,mpc8540-memory-controller";
74 reg = <0x2000 0x1000>;
75 interrupt-parent = <&mpic>;
79 L2: l2-cache-controller@20000 {
80 compatible = "fsl,mpc8540-l2-cache-controller";
81 reg = <0x20000 0x1000>;
82 cache-line-size = <32>;
83 cache-size = <0x40000>; // L2, 256K
84 interrupt-parent = <&mpic>;
92 compatible = "fsl-i2c";
95 interrupt-parent = <&mpic>;
99 compatible = "national,lm75";
104 compatible = "dallas,ds1337";
110 #address-cells = <1>;
112 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
114 ranges = <0x0 0x21100 0x200>;
117 compatible = "fsl,mpc8560-dma-channel",
118 "fsl,eloplus-dma-channel";
121 interrupt-parent = <&mpic>;
125 compatible = "fsl,mpc8560-dma-channel",
126 "fsl,eloplus-dma-channel";
129 interrupt-parent = <&mpic>;
133 compatible = "fsl,mpc8560-dma-channel",
134 "fsl,eloplus-dma-channel";
137 interrupt-parent = <&mpic>;
141 compatible = "fsl,mpc8560-dma-channel",
142 "fsl,eloplus-dma-channel";
145 interrupt-parent = <&mpic>;
150 enet0: ethernet@24000 {
151 #address-cells = <1>;
154 device_type = "network";
156 compatible = "gianfar";
157 reg = <0x24000 0x1000>;
158 ranges = <0x0 0x24000 0x1000>;
159 local-mac-address = [ 00 00 00 00 00 00 ];
160 interrupts = <29 2 30 2 34 2>;
161 interrupt-parent = <&mpic>;
162 tbi-handle = <&tbi0>;
163 phy-handle = <&phy2>;
166 #address-cells = <1>;
168 compatible = "fsl,gianfar-mdio";
171 phy1: ethernet-phy@1 {
172 interrupt-parent = <&mpic>;
176 phy2: ethernet-phy@2 {
177 interrupt-parent = <&mpic>;
181 phy3: ethernet-phy@3 {
182 interrupt-parent = <&mpic>;
188 device_type = "tbi-phy";
193 enet1: ethernet@25000 {
194 #address-cells = <1>;
197 device_type = "network";
199 compatible = "gianfar";
200 reg = <0x25000 0x1000>;
201 ranges = <0x0 0x25000 0x1000>;
202 local-mac-address = [ 00 00 00 00 00 00 ];
203 interrupts = <35 2 36 2 40 2>;
204 interrupt-parent = <&mpic>;
205 tbi-handle = <&tbi1>;
206 phy-handle = <&phy1>;
209 #address-cells = <1>;
211 compatible = "fsl,gianfar-tbi";
216 device_type = "tbi-phy";
222 interrupt-controller;
223 #address-cells = <0>;
224 #interrupt-cells = <2>;
225 reg = <0x40000 0x40000>;
226 device_type = "open-pic";
227 compatible = "chrp,open-pic";
231 #address-cells = <1>;
233 compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
234 reg = <0x919c0 0x30>;
238 #address-cells = <1>;
240 ranges = <0 0x80000 0x10000>;
243 compatible = "fsl,cpm-muram-data";
244 reg = <0 0x4000 0x9000 0x2000>;
249 compatible = "fsl,mpc8560-brg",
252 reg = <0x919f0 0x10 0x915f0 0x10>;
253 clock-frequency = <0>;
257 interrupt-controller;
258 #address-cells = <0>;
259 #interrupt-cells = <2>;
261 interrupt-parent = <&mpic>;
262 reg = <0x90c00 0x80>;
263 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
266 serial0: serial@91a00 {
267 device_type = "serial";
268 compatible = "fsl,mpc8560-scc-uart",
270 reg = <0x91a00 0x20 0x88000 0x100>;
272 fsl,cpm-command = <0x800000>;
273 current-speed = <115200>;
275 interrupt-parent = <&cpmpic>;
278 serial1: serial@91a20 {
279 device_type = "serial";
280 compatible = "fsl,mpc8560-scc-uart",
282 reg = <0x91a20 0x20 0x88100 0x100>;
284 fsl,cpm-command = <0x4a00000>;
285 current-speed = <115200>;
287 interrupt-parent = <&cpmpic>;
290 enet2: ethernet@91340 {
291 device_type = "network";
292 compatible = "fsl,mpc8560-fcc-enet",
294 reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
295 local-mac-address = [ 00 00 00 00 00 00 ];
296 fsl,cpm-command = <0x1a400300>;
298 interrupt-parent = <&cpmpic>;
299 phy-handle = <&phy3>;
305 compatible = "fsl,mpc8560-localbus", "fsl,pq3-localbus",
307 #address-cells = <2>;
309 reg = <0xe0005000 0x100>; // BRx, ORx, etc.
310 interrupt-parent = <&mpic>;
314 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
315 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
316 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527)
320 #address-cells = <1>;
322 compatible = "cfi-flash";
323 reg = <1 0x0 0x8000000>;
329 reg = <0x00000000 0x00200000>;
333 reg = <0x00200000 0x00300000>;
337 reg = <0x00500000 0x07a00000>;
341 reg = <0x07f00000 0x00040000>;
345 reg = <0x07f40000 0x00040000>;
349 reg = <0x07f80000 0x00080000>;
354 /* Note: CAN support needs be enabled in U-Boot */
356 compatible = "intel,82527"; // Bosch CC770
359 interrupt-parent = <&mpic>;
363 compatible = "intel,82527"; // Bosch CC770
364 reg = <2 0x100 0x100>;
366 interrupt-parent = <&mpic>;
371 #interrupt-cells = <1>;
373 #address-cells = <3>;
374 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
376 reg = <0xe0008000 0x1000>;
377 clock-frequency = <66666666>;
378 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
381 0xe000 0 0 1 &mpic 2 1
382 0xe000 0 0 2 &mpic 3 1
383 0xe000 0 0 3 &mpic 6 1
384 0xe000 0 0 4 &mpic 5 1
387 0x5800 0 0 1 &mpic 6 1
388 0x5800 0 0 2 &mpic 5 1
391 interrupt-parent = <&mpic>;
394 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
395 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;