2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
15 * Copyright SUSE Linux Products GmbH 2010
17 * Authors: Alexander Graf <agraf@suse.de>
20 /* Real mode helpers */
22 #include <asm/asm-compat.h>
23 #include <asm/feature-fixups.h>
25 #if defined(CONFIG_PPC_BOOK3S_64)
27 #define GET_SHADOW_VCPU(reg) \
30 #elif defined(CONFIG_PPC_BOOK3S_32)
32 #define GET_SHADOW_VCPU(reg) \
34 lwz reg, (THREAD + THREAD_KVM_SVCPU)(reg); \
39 /* Disable for nested KVM */
40 #define USE_QUICK_LAST_INST
43 /* Get helper functions for subarch specific functionality */
45 #if defined(CONFIG_PPC_BOOK3S_64)
46 #include "book3s_64_slb.S"
47 #elif defined(CONFIG_PPC_BOOK3S_32)
48 #include "book3s_32_sr.S"
51 /******************************************************************************
55 *****************************************************************************/
57 .global kvmppc_handler_trampoline_enter
58 kvmppc_handler_trampoline_enter:
65 * R4 = guest shadow MSR
66 * R5 = normal host MSR
67 * R6 = current host MSR (EE, IR, DR off)
68 * LR = highmem guest exit code
69 * all other volatile GPRS = free
70 * SVCPU[CR] = guest CR
71 * SVCPU[XER] = guest XER
72 * SVCPU[CTR] = guest CTR
73 * SVCPU[LR] = guest LR
76 /* r3 = shadow vcpu */
79 /* Save guest exit handler address and MSR */
81 PPC_STL r0, HSTATE_VMHANDLER(r3)
82 PPC_STL r5, HSTATE_HOST_MSR(r3)
84 /* Save R1/R2 in the PACA (64-bit) or shadow_vcpu (32-bit) */
85 PPC_STL r1, HSTATE_HOST_R1(r3)
86 PPC_STL r2, HSTATE_HOST_R2(r3)
88 /* Activate guest mode, so faults get handled by KVM */
89 li r11, KVM_GUEST_MODE_GUEST
90 stb r11, HSTATE_IN_GUEST(r3)
92 /* Switch to guest segment. This is subarch specific. */
95 #ifdef CONFIG_PPC_BOOK3S_64
99 std r8, HSTATE_HOST_FSCR(r13)
100 /* Set FSCR during guest execution */
101 ld r9, SVCPU_SHADOW_FSCR(r13)
103 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
105 /* Some guests may need to have dcbz set to 32 byte length.
107 * Usually we ensure that by patching the guest's instructions
108 * to trap on dcbz and emulate it in the hypervisor.
110 * If we can, we should tell the CPU to use 32 byte dcbz though,
111 * because that's a lot faster.
113 lbz r0, HSTATE_RESTORE_HID5(r3)
118 ori r0, r0, 0x80 /* XXX HID5_dcbz32 = 0x80 */
122 #endif /* CONFIG_PPC_BOOK3S_64 */
126 PPC_LL r8, SVCPU_CTR(r3)
127 PPC_LL r9, SVCPU_LR(r3)
128 lwz r10, SVCPU_CR(r3)
129 PPC_LL r11, SVCPU_XER(r3)
136 /* Move SRR0 and SRR1 into the respective regs */
137 PPC_LL r9, SVCPU_PC(r3)
138 /* First clear RI in our current MSR value */
142 PPC_LL r0, SVCPU_R0(r3)
143 PPC_LL r1, SVCPU_R1(r3)
144 PPC_LL r2, SVCPU_R2(r3)
145 PPC_LL r5, SVCPU_R5(r3)
146 PPC_LL r7, SVCPU_R7(r3)
147 PPC_LL r8, SVCPU_R8(r3)
148 PPC_LL r10, SVCPU_R10(r3)
149 PPC_LL r11, SVCPU_R11(r3)
150 PPC_LL r12, SVCPU_R12(r3)
151 PPC_LL r13, SVCPU_R13(r3)
157 PPC_LL r4, SVCPU_R4(r3)
158 PPC_LL r6, SVCPU_R6(r3)
159 PPC_LL r9, SVCPU_R9(r3)
160 PPC_LL r3, (SVCPU_R3)(r3)
163 kvmppc_handler_trampoline_enter_end:
167 /******************************************************************************
171 *****************************************************************************/
173 .global kvmppc_interrupt_pr
175 /* 64-bit entry. Register usage at this point:
177 * SPRG_SCRATCH0 = guest R13
178 * R12 = (guest CR << 32) | exit handler id
180 * HSTATE.SCRATCH0 = guest R12
181 * HSTATE.SCRATCH1 = guest CTR if RELOCATABLE
184 /* Match 32-bit entry */
185 #ifdef CONFIG_RELOCATABLE
186 std r9, HSTATE_SCRATCH2(r13)
187 ld r9, HSTATE_SCRATCH1(r13)
189 ld r9, HSTATE_SCRATCH2(r13)
191 rotldi r12, r12, 32 /* Flip R12 halves for stw */
192 stw r12, HSTATE_SCRATCH1(r13) /* CR is now in the low half */
193 srdi r12, r12, 32 /* shift trap into low half */
196 .global kvmppc_handler_trampoline_exit
197 kvmppc_handler_trampoline_exit:
198 /* Register usage at this point:
200 * SPRG_SCRATCH0 = guest R13
201 * R12 = exit handler id
202 * R13 = shadow vcpu (32-bit) or PACA (64-bit)
203 * HSTATE.SCRATCH0 = guest R12
204 * HSTATE.SCRATCH1 = guest CR
209 PPC_STL r0, SVCPU_R0(r13)
210 PPC_STL r1, SVCPU_R1(r13)
211 PPC_STL r2, SVCPU_R2(r13)
212 PPC_STL r3, SVCPU_R3(r13)
213 PPC_STL r4, SVCPU_R4(r13)
214 PPC_STL r5, SVCPU_R5(r13)
215 PPC_STL r6, SVCPU_R6(r13)
216 PPC_STL r7, SVCPU_R7(r13)
217 PPC_STL r8, SVCPU_R8(r13)
218 PPC_STL r9, SVCPU_R9(r13)
219 PPC_STL r10, SVCPU_R10(r13)
220 PPC_STL r11, SVCPU_R11(r13)
222 /* Restore R1/R2 so we can handle faults */
223 PPC_LL r1, HSTATE_HOST_R1(r13)
224 PPC_LL r2, HSTATE_HOST_R2(r13)
226 /* Save guest PC and MSR */
236 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
241 PPC_STL r3, SVCPU_PC(r13)
242 PPC_STL r4, SVCPU_SHADOW_SRR1(r13)
244 /* Get scratch'ed off registers */
246 PPC_LL r8, HSTATE_SCRATCH0(r13)
247 lwz r7, HSTATE_SCRATCH1(r13)
249 PPC_STL r9, SVCPU_R13(r13)
250 PPC_STL r8, SVCPU_R12(r13)
251 stw r7, SVCPU_CR(r13)
253 /* Save more register state */
261 PPC_STL r5, SVCPU_XER(r13)
262 PPC_STL r6, SVCPU_FAULT_DAR(r13)
263 stw r7, SVCPU_FAULT_DSISR(r13)
264 PPC_STL r8, SVCPU_CTR(r13)
265 PPC_STL r9, SVCPU_LR(r13)
268 * In order for us to easily get the last instruction,
269 * we got the #vmexit at, we exploit the fact that the
270 * virtual layout is still the same here, so we can just
271 * ld from the guest's PC address
274 /* We only load the last instruction when it's safe */
275 cmpwi r12, BOOK3S_INTERRUPT_DATA_STORAGE
277 cmpwi r12, BOOK3S_INTERRUPT_PROGRAM
279 cmpwi r12, BOOK3S_INTERRUPT_SYSCALL
280 beq ld_last_prev_inst
281 cmpwi r12, BOOK3S_INTERRUPT_ALIGNMENT
285 cmpwi r12, BOOK3S_INTERRUPT_H_EMUL_ASSIST
287 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
289 cmpwi r12, BOOK3S_INTERRUPT_FAC_UNAVAIL
291 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
300 /* Save off the guest instruction we're at */
302 /* In case lwz faults */
303 li r0, KVM_INST_FETCH_FAILED
305 #ifdef USE_QUICK_LAST_INST
307 /* Set guest mode to 'jump over instruction' so if lwz faults
308 * we'll just continue at the next IP. */
309 li r9, KVM_GUEST_MODE_SKIP
310 stb r9, HSTATE_IN_GUEST(r13)
312 /* 1) enable paging for data */
314 ori r11, r9, MSR_DR /* Enable paging for data */
317 /* 2) fetch the instruction */
319 /* 3) disable paging again */
324 stw r0, SVCPU_LAST_INST(r13)
328 /* Unset guest mode */
329 li r9, KVM_GUEST_MODE_NONE
330 stb r9, HSTATE_IN_GUEST(r13)
332 /* Switch back to host MMU */
335 #ifdef CONFIG_PPC_BOOK3S_64
337 lbz r5, HSTATE_RESTORE_HID5(r13)
349 /* Save guest FSCR on a FAC_UNAVAIL interrupt */
350 cmpwi r12, BOOK3S_INTERRUPT_FAC_UNAVAIL
353 std r7, SVCPU_SHADOW_FSCR(r13)
355 /* Restore host FSCR */
356 ld r8, HSTATE_HOST_FSCR(r13)
358 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
360 #endif /* CONFIG_PPC_BOOK3S_64 */
363 * For some interrupts, we need to call the real Linux
364 * handler, so it can do work for us. This has to happen
365 * as if the interrupt arrived from the kernel though,
366 * so let's fake it here where most state is restored.
368 * Having set up SRR0/1 with the address where we want
369 * to continue with relocation on (potentially in module
370 * space), we either just go straight there with rfi[d],
371 * or we jump to an interrupt handler if there is an
372 * interrupt to be handled first. In the latter case,
373 * the rfi[d] at the end of the interrupt handler will
374 * get us back to where we want to continue.
377 /* Register usage at this point:
381 * R10 = raw exit handler id
382 * R12 = exit handler id
383 * R13 = shadow vcpu (32-bit) or PACA (64-bit)
388 PPC_LL r6, HSTATE_HOST_MSR(r13)
389 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
391 * We don't want to change MSR[TS] bits via rfi here.
392 * The actual TM handling logic will be in host with
393 * recovered DR/IR bits after HSTATE_VMHANDLER.
394 * And MSR_TM can be enabled in HOST_MSR so rfid may
395 * not suppress this change and can lead to exception.
396 * Manually set MSR to prevent TS state change here.
399 rldicl r7, r7, 64 - MSR_TS_S_LG, 62
400 rldimi r6, r7, MSR_TS_S_LG, 63 - MSR_TS_T_LG
402 PPC_LL r8, HSTATE_VMHANDLER(r13)
409 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
411 1: /* Restore host msr -> SRR1 */
413 /* Load highmem handler address */
416 /* RFI into the highmem handler, or jump to interrupt handler */
417 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
418 beqa BOOK3S_INTERRUPT_EXTERNAL
419 cmpwi r12, BOOK3S_INTERRUPT_DECREMENTER
420 beqa BOOK3S_INTERRUPT_DECREMENTER
421 cmpwi r12, BOOK3S_INTERRUPT_PERFMON
422 beqa BOOK3S_INTERRUPT_PERFMON
423 cmpwi r12, BOOK3S_INTERRUPT_DOORBELL
424 beqa BOOK3S_INTERRUPT_DOORBELL
427 kvmppc_handler_trampoline_exit_end: