2 * Copyright 2017 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License, version 2, as
6 * published by the Free Software Foundation.
9 #include <linux/kvm_host.h>
11 #include <asm/kvm_ppc.h>
12 #include <asm/kvm_book3s.h>
13 #include <asm/kvm_book3s_64.h>
15 #include <asm/ppc-opcode.h>
18 * This handles the cases where the guest is in real suspend mode
19 * and we want to get back to the guest without dooming the transaction.
20 * The caller has checked that the guest is in real-suspend mode
21 * (MSR[TS] = S and the fake-suspend flag is not set).
23 int kvmhv_p9_tm_emulation_early(struct kvm_vcpu *vcpu)
25 u32 instr = vcpu->arch.emul_inst;
26 u64 newmsr, msr, bescr;
30 * rfid, rfebb, and mtmsrd encode bit 31 = 0 since it's a reserved bit
31 * in these instructions, so masking bit 31 out doesn't change these
32 * instructions. For the tsr. instruction if bit 31 = 0 then it is per
33 * ISA an invalid form, however P9 UM, in section 4.6.10 Book II Invalid
34 * Forms, informs specifically that ignoring bit 31 is an acceptable way
35 * to handle TM-related invalid forms that have bit 31 = 0. Moreover,
36 * for emulation purposes both forms (w/ and wo/ bit 31 set) can
37 * generate a softpatch interrupt. Hence both forms are handled below
38 * for tsr. to make them behave the same way.
40 switch (instr & PO_XOP_OPCODE_MASK) {
42 /* XXX do we need to check for PR=0 here? */
43 newmsr = vcpu->arch.shregs.srr1;
44 /* should only get here for Sx -> T1 transition */
45 if (!(MSR_TM_TRANSACTIONAL(newmsr) && (newmsr & MSR_TM)))
47 newmsr = sanitize_msr(newmsr);
48 vcpu->arch.shregs.msr = newmsr;
49 vcpu->arch.cfar = vcpu->arch.regs.nip - 4;
50 vcpu->arch.regs.nip = vcpu->arch.shregs.srr0;
54 /* check for PR=1 and arch 2.06 bit set in PCR */
55 msr = vcpu->arch.shregs.msr;
56 if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206))
58 /* check EBB facility is available */
59 if (!(vcpu->arch.hfscr & HFSCR_EBB) ||
60 ((msr & MSR_PR) && !(mfspr(SPRN_FSCR) & FSCR_EBB)))
62 bescr = mfspr(SPRN_BESCR);
63 /* expect to see a S->T transition requested */
64 if (((bescr >> 30) & 3) != 2)
67 if (instr & (1 << 11))
69 mtspr(SPRN_BESCR, bescr);
70 msr = (msr & ~MSR_TS_MASK) | MSR_TS_T;
71 vcpu->arch.shregs.msr = msr;
72 vcpu->arch.cfar = vcpu->arch.regs.nip - 4;
73 vcpu->arch.regs.nip = mfspr(SPRN_EBBRR);
77 /* XXX do we need to check for PR=0 here? */
78 rs = (instr >> 21) & 0x1f;
79 newmsr = kvmppc_get_gpr(vcpu, rs);
80 msr = vcpu->arch.shregs.msr;
81 /* check this is a Sx -> T1 transition */
82 if (!(MSR_TM_TRANSACTIONAL(newmsr) && (newmsr & MSR_TM)))
84 /* mtmsrd doesn't change LE */
85 newmsr = (newmsr & ~MSR_LE) | (msr & MSR_LE);
86 newmsr = sanitize_msr(newmsr);
87 vcpu->arch.shregs.msr = newmsr;
90 /* ignore bit 31, see comment above */
91 case (PPC_INST_TSR & PO_XOP_OPCODE_MASK):
92 /* we know the MSR has the TS field = S (0b01) here */
93 msr = vcpu->arch.shregs.msr;
94 /* check for PR=1 and arch 2.06 bit set in PCR */
95 if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206))
97 /* check for TM disabled in the HFSCR or MSR */
98 if (!(vcpu->arch.hfscr & HFSCR_TM) || !(msr & MSR_TM))
100 /* L=1 => tresume => set TS to T (0b10) */
101 if (instr & (1 << 21))
102 vcpu->arch.shregs.msr = (msr & ~MSR_TS_MASK) | MSR_TS_T;
103 /* Set CR0 to 0b0010 */
104 vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |
113 * This is called when we are returning to a guest in TM transactional
114 * state. We roll the guest state back to the checkpointed state.
116 void kvmhv_emulate_tm_rollback(struct kvm_vcpu *vcpu)
118 vcpu->arch.shregs.msr &= ~MSR_TS_MASK; /* go to N state */
119 vcpu->arch.regs.nip = vcpu->arch.tfhar;
120 copy_from_checkpoint(vcpu);
121 vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) | 0xa0000000;