2 * Copyright (C) 2016 Imagination Technologies
3 * Author: Paul Burton <paul.burton@mips.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
11 #define pr_fmt(fmt) "sead3: " fmt
13 #include <linux/errno.h>
14 #include <linux/libfdt.h>
15 #include <linux/printk.h>
16 #include <linux/sizes.h>
18 #include <asm/fw/fw.h>
20 #include <asm/machine.h>
21 #include <asm/yamon-dt.h>
23 #define SEAD_CONFIG CKSEG1ADDR(0x1b100110)
24 #define SEAD_CONFIG_GIC_PRESENT BIT(1)
26 #define MIPS_REVISION CKSEG1ADDR(0x1fc00010)
27 #define MIPS_REVISION_MACHINE (0xf << 4)
28 #define MIPS_REVISION_MACHINE_SEAD3 (0x4 << 4)
31 * Maximum 384MB RAM at physical address 0, preceding any I/O.
33 static struct yamon_mem_region mem_regions[] __initdata = {
35 { 0, SZ_256M + SZ_128M },
39 static __init bool sead3_detect(void)
43 rev = __raw_readl((void *)MIPS_REVISION);
44 return (rev & MIPS_REVISION_MACHINE) == MIPS_REVISION_MACHINE_SEAD3;
47 static __init int append_memory(void *fdt)
49 return yamon_dt_append_memory(fdt, mem_regions);
52 static __init int remove_gic(void *fdt)
54 const unsigned int cpu_ehci_int = 2;
55 const unsigned int cpu_uart_int = 4;
56 const unsigned int cpu_eth_int = 6;
57 int gic_off, cpu_off, uart_off, eth_off, ehci_off, err;
58 uint32_t cfg, cpu_phandle;
60 /* leave the GIC node intact if a GIC is present */
61 cfg = __raw_readl((uint32_t *)SEAD_CONFIG);
62 if (cfg & SEAD_CONFIG_GIC_PRESENT)
65 gic_off = fdt_node_offset_by_compatible(fdt, -1, "mti,gic");
67 pr_err("unable to find DT GIC node: %d\n", gic_off);
71 err = fdt_nop_node(fdt, gic_off);
73 pr_err("unable to nop GIC node\n");
77 cpu_off = fdt_node_offset_by_compatible(fdt, -1,
78 "mti,cpu-interrupt-controller");
80 pr_err("unable to find CPU intc node: %d\n", cpu_off);
84 cpu_phandle = fdt_get_phandle(fdt, cpu_off);
86 pr_err("unable to get CPU intc phandle\n");
90 uart_off = fdt_node_offset_by_compatible(fdt, -1, "ns16550a");
91 while (uart_off >= 0) {
92 err = fdt_setprop_u32(fdt, uart_off, "interrupt-parent",
95 pr_warn("unable to set UART interrupt-parent: %d\n",
100 err = fdt_setprop_u32(fdt, uart_off, "interrupts",
103 pr_err("unable to set UART interrupts property: %d\n",
108 uart_off = fdt_node_offset_by_compatible(fdt, uart_off,
111 if (uart_off != -FDT_ERR_NOTFOUND) {
112 pr_err("error searching for UART DT node: %d\n", uart_off);
116 eth_off = fdt_node_offset_by_compatible(fdt, -1, "smsc,lan9115");
118 pr_err("unable to find ethernet DT node: %d\n", eth_off);
122 err = fdt_setprop_u32(fdt, eth_off, "interrupt-parent", cpu_phandle);
124 pr_err("unable to set ethernet interrupt-parent: %d\n", err);
128 err = fdt_setprop_u32(fdt, eth_off, "interrupts", cpu_eth_int);
130 pr_err("unable to set ethernet interrupts property: %d\n", err);
134 ehci_off = fdt_node_offset_by_compatible(fdt, -1, "generic-ehci");
136 pr_err("unable to find EHCI DT node: %d\n", ehci_off);
140 err = fdt_setprop_u32(fdt, ehci_off, "interrupt-parent", cpu_phandle);
142 pr_err("unable to set EHCI interrupt-parent: %d\n", err);
146 err = fdt_setprop_u32(fdt, ehci_off, "interrupts", cpu_ehci_int);
148 pr_err("unable to set EHCI interrupts property: %d\n", err);
155 static const struct mips_fdt_fixup sead3_fdt_fixups[] __initconst = {
156 { yamon_dt_append_cmdline, "append command line" },
157 { append_memory, "append memory" },
158 { remove_gic, "remove GIC when not present" },
159 { yamon_dt_serial_config, "append serial configuration" },
163 static __init const void *sead3_fixup_fdt(const void *fdt,
164 const void *match_data)
166 static unsigned char fdt_buf[16 << 10] __initdata;
169 if (fdt_check_header(fdt))
172 /* if this isn't SEAD3, something went wrong */
173 BUG_ON(fdt_node_check_compatible(fdt, 0, "mti,sead-3"));
177 err = apply_mips_fdt_fixups(fdt_buf, sizeof(fdt_buf),
178 fdt, sead3_fdt_fixups);
180 panic("Unable to fixup FDT: %d", err);
185 static __init unsigned int sead3_measure_hpt_freq(void)
187 void __iomem *status_reg = (void __iomem *)0xbf000410;
188 unsigned int freq, orig, tick = 0;
191 local_irq_save(flags);
193 orig = readl(status_reg) & 0x2; /* get original sample */
194 /* wait for transition */
195 while ((readl(status_reg) & 0x2) == orig)
197 orig = orig ^ 0x2; /* flip the bit */
201 /* wait 1 second (the sampling clock transitions every 10ms) */
203 /* wait for transition */
204 while ((readl(status_reg) & 0x2) == orig)
206 orig = orig ^ 0x2; /* flip the bit */
210 freq = read_c0_count();
212 local_irq_restore(flags);
217 extern char __dtb_sead3_begin[];
219 MIPS_MACHINE(sead3) = {
220 .fdt = __dtb_sead3_begin,
221 .detect = sead3_detect,
222 .fixup_fdt = sead3_fixup_fdt,
223 .measure_hpt_freq = sead3_measure_hpt_freq,