2 * TI DaVinci EVM board support
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/platform_device.h>
15 #include <linux/gpio.h>
16 #include <linux/i2c.h>
17 #include <linux/platform_data/pcf857x.h>
18 #include <linux/platform_data/at24.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/rawnand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/mtd/physmap.h>
23 #include <linux/phy.h>
24 #include <linux/clk.h>
25 #include <linux/videodev2.h>
26 #include <linux/v4l2-dv-timings.h>
27 #include <linux/export.h>
28 #include <linux/leds.h>
30 #include <media/i2c/tvp514x.h>
32 #include <asm/mach-types.h>
33 #include <asm/mach/arch.h>
35 #include <mach/common.h>
36 #include <linux/platform_data/i2c-davinci.h>
37 #include <mach/serial.h>
39 #include <linux/platform_data/mtd-davinci.h>
40 #include <linux/platform_data/mmc-davinci.h>
41 #include <linux/platform_data/usb-davinci.h>
42 #include <linux/platform_data/mtd-davinci-aemif.h>
46 #define DM644X_EVM_PHY_ID "davinci_mdio-0:01"
47 #define LXT971_PHY_ID (0x001378e2)
48 #define LXT971_PHY_MASK (0xfffffff0)
50 static struct mtd_partition davinci_evm_norflash_partitions[] = {
51 /* bootloader (UBL, U-Boot, etc) in first 5 sectors */
56 .mask_flags = MTD_WRITEABLE, /* force read-only */
58 /* bootloader params in the next 1 sectors */
61 .offset = MTDPART_OFS_APPEND,
68 .offset = MTDPART_OFS_APPEND,
75 .offset = MTDPART_OFS_APPEND,
76 .size = MTDPART_SIZ_FULL,
81 static struct physmap_flash_data davinci_evm_norflash_data = {
83 .parts = davinci_evm_norflash_partitions,
84 .nr_parts = ARRAY_SIZE(davinci_evm_norflash_partitions),
87 /* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
88 * limits addresses to 16M, so using addresses past 16M will wrap */
89 static struct resource davinci_evm_norflash_resource = {
90 .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
91 .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
92 .flags = IORESOURCE_MEM,
95 static struct platform_device davinci_evm_norflash_device = {
96 .name = "physmap-flash",
99 .platform_data = &davinci_evm_norflash_data,
102 .resource = &davinci_evm_norflash_resource,
105 /* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks).
106 * It may used instead of the (default) NOR chip to boot, using TI's
107 * tools to install the secondary boot loader (UBL) and U-Boot.
109 static struct mtd_partition davinci_evm_nandflash_partition[] = {
110 /* Bootloader layout depends on whose u-boot is installed, but we
111 * can hide all the details.
112 * - block 0 for u-boot environment ... in mainline u-boot
113 * - block 1 for UBL (plus up to four backup copies in blocks 2..5)
114 * - blocks 6...? for u-boot
115 * - blocks 16..23 for u-boot environment ... in TI's u-boot
118 .name = "bootloader",
120 .size = SZ_256K + SZ_128K,
121 .mask_flags = MTD_WRITEABLE, /* force read-only */
126 .offset = MTDPART_OFS_APPEND,
130 /* File system (older GIT kernels started this on the 5MB mark) */
132 .name = "filesystem",
133 .offset = MTDPART_OFS_APPEND,
134 .size = MTDPART_SIZ_FULL,
137 /* A few blocks at end hold a flash BBT ... created by TI's CCS
138 * using flashwriter_nand.out, but ignored by TI's versions of
139 * Linux and u-boot. We boot faster by using them.
143 static struct davinci_aemif_timing davinci_evm_nandflash_timing = {
153 static struct davinci_nand_pdata davinci_evm_nandflash_data = {
154 .parts = davinci_evm_nandflash_partition,
155 .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
156 .ecc_mode = NAND_ECC_HW,
158 .bbt_options = NAND_BBT_USE_FLASH,
159 .timing = &davinci_evm_nandflash_timing,
162 static struct resource davinci_evm_nandflash_resource[] = {
164 .start = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
165 .end = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
166 .flags = IORESOURCE_MEM,
168 .start = DM644X_ASYNC_EMIF_CONTROL_BASE,
169 .end = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
170 .flags = IORESOURCE_MEM,
174 static struct platform_device davinci_evm_nandflash_device = {
175 .name = "davinci_nand",
178 .platform_data = &davinci_evm_nandflash_data,
180 .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource),
181 .resource = davinci_evm_nandflash_resource,
184 static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
186 static struct platform_device davinci_fb_device = {
190 .dma_mask = &davinci_fb_dma_mask,
191 .coherent_dma_mask = DMA_BIT_MASK(32),
196 static struct tvp514x_platform_data dm644xevm_tvp5146_pdata = {
202 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
203 /* Inputs available at the TVP5146 */
204 static struct v4l2_input dm644xevm_tvp5146_inputs[] = {
208 .type = V4L2_INPUT_TYPE_CAMERA,
209 .std = TVP514X_STD_ALL,
214 .type = V4L2_INPUT_TYPE_CAMERA,
215 .std = TVP514X_STD_ALL,
220 * this is the route info for connecting each input to decoder
221 * ouput that goes to vpfe. There is a one to one correspondence
222 * with tvp5146_inputs
224 static struct vpfe_route dm644xevm_tvp5146_routes[] = {
226 .input = INPUT_CVBS_VI2B,
227 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
230 .input = INPUT_SVIDEO_VI2C_VI1C,
231 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
235 static struct vpfe_subdev_info dm644xevm_vpfe_sub_devs[] = {
239 .num_inputs = ARRAY_SIZE(dm644xevm_tvp5146_inputs),
240 .inputs = dm644xevm_tvp5146_inputs,
241 .routes = dm644xevm_tvp5146_routes,
244 .if_type = VPFE_BT656,
245 .hdpol = VPFE_PINPOL_POSITIVE,
246 .vdpol = VPFE_PINPOL_POSITIVE,
249 I2C_BOARD_INFO("tvp5146", 0x5d),
250 .platform_data = &dm644xevm_tvp5146_pdata,
255 static struct vpfe_config dm644xevm_capture_cfg = {
256 .num_subdevs = ARRAY_SIZE(dm644xevm_vpfe_sub_devs),
258 .sub_devs = dm644xevm_vpfe_sub_devs,
259 .card_name = "DM6446 EVM",
260 .ccdc = "DM6446 CCDC",
263 static struct platform_device rtc_dev = {
264 .name = "rtc_davinci_evm",
268 /*----------------------------------------------------------------------*/
274 #define PCF_Uxx_BASE(x) (DAVINCI_N_GPIO + ((x) * 8))
279 static struct gpio_led evm_leds[] = {
280 { .name = "DS8", .active_low = 1,
281 .default_trigger = "heartbeat", },
282 { .name = "DS7", .active_low = 1, },
283 { .name = "DS6", .active_low = 1, },
284 { .name = "DS5", .active_low = 1, },
285 { .name = "DS4", .active_low = 1, },
286 { .name = "DS3", .active_low = 1, },
287 { .name = "DS2", .active_low = 1,
288 .default_trigger = "mmc0", },
289 { .name = "DS1", .active_low = 1,
290 .default_trigger = "disk-activity", },
293 static const struct gpio_led_platform_data evm_led_data = {
294 .num_leds = ARRAY_SIZE(evm_leds),
298 static struct platform_device *evm_led_dev;
301 evm_led_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
303 struct gpio_led *leds = evm_leds;
311 /* what an extremely annoying way to be forced to handle
312 * device unregistration ...
314 evm_led_dev = platform_device_alloc("leds-gpio", 0);
315 platform_device_add_data(evm_led_dev,
316 &evm_led_data, sizeof evm_led_data);
318 evm_led_dev->dev.parent = &client->dev;
319 status = platform_device_add(evm_led_dev);
321 platform_device_put(evm_led_dev);
328 evm_led_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
331 platform_device_unregister(evm_led_dev);
337 static struct pcf857x_platform_data pcf_data_u2 = {
338 .gpio_base = PCF_Uxx_BASE(0),
339 .setup = evm_led_setup,
340 .teardown = evm_led_teardown,
344 /* U18 - A/V clock generator and user switch */
349 sw_show(struct device *d, struct device_attribute *a, char *buf)
351 char *s = gpio_get_value_cansleep(sw_gpio) ? "on\n" : "off\n";
357 static DEVICE_ATTR(user_sw, S_IRUGO, sw_show, NULL);
360 evm_u18_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
364 /* export dip switch option */
366 status = gpio_request(sw_gpio, "user_sw");
368 status = gpio_direction_input(sw_gpio);
370 status = device_create_file(&client->dev, &dev_attr_user_sw);
376 /* audio PLL: 48 kHz (vs 44.1 or 32), single rate (vs double) */
377 gpio_request(gpio + 3, "pll_fs2");
378 gpio_direction_output(gpio + 3, 0);
380 gpio_request(gpio + 2, "pll_fs1");
381 gpio_direction_output(gpio + 2, 0);
383 gpio_request(gpio + 1, "pll_sr");
384 gpio_direction_output(gpio + 1, 0);
390 evm_u18_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
397 device_remove_file(&client->dev, &dev_attr_user_sw);
403 static struct pcf857x_platform_data pcf_data_u18 = {
404 .gpio_base = PCF_Uxx_BASE(1),
405 .n_latch = (1 << 3) | (1 << 2) | (1 << 1),
406 .setup = evm_u18_setup,
407 .teardown = evm_u18_teardown,
411 /* U35 - various I/O signals used to manage USB, CF, ATA, etc */
414 evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
416 /* p0 = nDRV_VBUS (initial: don't supply it) */
417 gpio_request(gpio + 0, "nDRV_VBUS");
418 gpio_direction_output(gpio + 0, 1);
421 gpio_request(gpio + 1, "VDDIMX_EN");
422 gpio_direction_output(gpio + 1, 1);
425 gpio_request(gpio + 2, "VLYNQ_EN");
426 gpio_direction_output(gpio + 2, 1);
428 /* p3 = n3V3_CF_RESET (initial: stay in reset) */
429 gpio_request(gpio + 3, "nCF_RESET");
430 gpio_direction_output(gpio + 3, 0);
434 /* p5 = 1V8_WLAN_RESET (initial: stay in reset) */
435 gpio_request(gpio + 5, "WLAN_RESET");
436 gpio_direction_output(gpio + 5, 1);
438 /* p6 = nATA_SEL (initial: select) */
439 gpio_request(gpio + 6, "nATA_SEL");
440 gpio_direction_output(gpio + 6, 0);
442 /* p7 = nCF_SEL (initial: deselect) */
443 gpio_request(gpio + 7, "nCF_SEL");
444 gpio_direction_output(gpio + 7, 1);
450 evm_u35_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
462 static struct pcf857x_platform_data pcf_data_u35 = {
463 .gpio_base = PCF_Uxx_BASE(2),
464 .setup = evm_u35_setup,
465 .teardown = evm_u35_teardown,
468 /*----------------------------------------------------------------------*/
470 /* Most of this EEPROM is unused, but U-Boot uses some data:
471 * - 0x7f00, 6 bytes Ethernet Address
472 * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
473 * - ... newer boards may have more
476 static struct at24_platform_data eeprom_info = {
477 .byte_len = (256*1024) / 8,
479 .flags = AT24_FLAG_ADDR16,
480 .setup = davinci_get_mac_addr,
481 .context = (void *)0x7f00,
485 * MSP430 supports RTC, card detection, input from IR remote, and
486 * a bit more. It triggers interrupts on GPIO(7) from pressing
487 * buttons on the IR remote, and for card detect switches.
489 static struct i2c_client *dm6446evm_msp;
491 static int dm6446evm_msp_probe(struct i2c_client *client,
492 const struct i2c_device_id *id)
494 dm6446evm_msp = client;
498 static int dm6446evm_msp_remove(struct i2c_client *client)
500 dm6446evm_msp = NULL;
504 static const struct i2c_device_id dm6446evm_msp_ids[] = {
505 { "dm6446evm_msp", 0, },
506 { /* end of list */ },
509 static struct i2c_driver dm6446evm_msp_driver = {
510 .driver.name = "dm6446evm_msp",
511 .id_table = dm6446evm_msp_ids,
512 .probe = dm6446evm_msp_probe,
513 .remove = dm6446evm_msp_remove,
516 static int dm6444evm_msp430_get_pins(void)
518 static const char txbuf[2] = { 2, 4, };
520 struct i2c_msg msg[2] = {
524 .buf = (void __force *)txbuf,
537 msg[0].addr = dm6446evm_msp->addr;
538 msg[1].addr = dm6446evm_msp->addr;
540 /* Command 4 == get input state, returns port 2 and port3 data
541 * S Addr W [A] len=2 [A] cmd=4 [A]
542 * RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
544 status = i2c_transfer(dm6446evm_msp->adapter, msg, 2);
548 dev_dbg(&dm6446evm_msp->dev, "PINS: %4ph\n", buf);
550 return (buf[3] << 8) | buf[2];
553 static int dm6444evm_mmc_get_cd(int module)
555 int status = dm6444evm_msp430_get_pins();
557 return (status < 0) ? status : !(status & BIT(1));
560 static int dm6444evm_mmc_get_ro(int module)
562 int status = dm6444evm_msp430_get_pins();
564 return (status < 0) ? status : status & BIT(6 + 8);
567 static struct davinci_mmc_config dm6446evm_mmc_config = {
568 .get_cd = dm6444evm_mmc_get_cd,
569 .get_ro = dm6444evm_mmc_get_ro,
573 static struct i2c_board_info __initdata i2c_info[] = {
575 I2C_BOARD_INFO("dm6446evm_msp", 0x23),
578 I2C_BOARD_INFO("pcf8574", 0x38),
579 .platform_data = &pcf_data_u2,
582 I2C_BOARD_INFO("pcf8574", 0x39),
583 .platform_data = &pcf_data_u18,
586 I2C_BOARD_INFO("pcf8574", 0x3a),
587 .platform_data = &pcf_data_u35,
590 I2C_BOARD_INFO("24c256", 0x50),
591 .platform_data = &eeprom_info,
594 I2C_BOARD_INFO("tlv320aic33", 0x1b),
598 /* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz),
599 * which requires 100 usec of idle bus after i2c writes sent to it.
601 static struct davinci_i2c_platform_data i2c_pdata = {
602 .bus_freq = 20 /* kHz */,
603 .bus_delay = 100 /* usec */,
608 static void __init evm_init_i2c(void)
610 davinci_init_i2c(&i2c_pdata);
611 i2c_add_driver(&dm6446evm_msp_driver);
612 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
616 #define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
618 /* venc standard timings */
619 static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
622 .timings_type = VPBE_ENC_STD,
623 .std_id = V4L2_STD_NTSC,
628 .fps = {30000, 1001},
630 .upper_margin = 0x10,
634 .timings_type = VPBE_ENC_STD,
635 .std_id = V4L2_STD_PAL,
642 .upper_margin = 0x16,
646 /* venc dv preset timings */
647 static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {
650 .timings_type = VPBE_ENC_DV_TIMINGS,
651 .dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
658 .upper_margin = 0x20,
662 .timings_type = VPBE_ENC_DV_TIMINGS,
663 .dv_timings = V4L2_DV_BT_CEA_720X576P50,
670 .upper_margin = 0x30,
675 * The outputs available from VPBE + encoders. Keep the order same
676 * as that of encoders. First those from venc followed by that from
677 * encoders. Index in the output refers to index on a particular encoder.
678 * Driver uses this index to pass it to encoder when it supports more
679 * than one output. Userspace applications use index of the array to
682 static struct vpbe_output dm644xevm_vpbe_outputs[] = {
687 .type = V4L2_OUTPUT_TYPE_ANALOG,
689 .capabilities = V4L2_OUT_CAP_STD,
691 .subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME,
692 .default_mode = "ntsc",
693 .num_modes = ARRAY_SIZE(dm644xevm_enc_std_timing),
694 .modes = dm644xevm_enc_std_timing,
700 .type = V4L2_OUTPUT_TYPE_ANALOG,
701 .capabilities = V4L2_OUT_CAP_DV_TIMINGS,
703 .subdev_name = DM644X_VPBE_VENC_SUBDEV_NAME,
704 .default_mode = "480p59_94",
705 .num_modes = ARRAY_SIZE(dm644xevm_enc_preset_timing),
706 .modes = dm644xevm_enc_preset_timing,
710 static struct vpbe_config dm644xevm_display_cfg = {
711 .module_name = "dm644x-vpbe-display",
714 .module_name = DM644X_VPBE_OSD_SUBDEV_NAME,
717 .module_name = DM644X_VPBE_VENC_SUBDEV_NAME,
719 .num_outputs = ARRAY_SIZE(dm644xevm_vpbe_outputs),
720 .outputs = dm644xevm_vpbe_outputs,
723 static struct platform_device *davinci_evm_devices[] __initdata = {
729 davinci_evm_map_io(void)
734 static int davinci_phy_fixup(struct phy_device *phydev)
736 unsigned int control;
737 /* CRITICAL: Fix for increasing PHY signal drive strength for
738 * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
739 * signal strength was low causing TX to fail randomly. The
740 * fix is to Set bit 11 (Increased MII drive strength) of PHY
741 * register 26 (Digital Config register) on this phy. */
742 control = phy_read(phydev, 26);
743 phy_write(phydev, 26, (control | 0x800));
747 #define HAS_ATA (IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
748 IS_ENABLED(CONFIG_PATA_BK3710))
750 #define HAS_NOR IS_ENABLED(CONFIG_MTD_PHYSMAP)
752 #define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
754 static __init void davinci_evm_init(void)
757 struct clk *aemif_clk;
758 struct davinci_soc_info *soc_info = &davinci_soc_info;
760 ret = dm644x_gpio_register();
762 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
764 aemif_clk = clk_get(NULL, "aemif");
765 clk_prepare_enable(aemif_clk);
768 if (HAS_NAND || HAS_NOR)
769 pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n"
770 "\tDisable IDE for NAND/NOR support\n");
772 } else if (HAS_NAND || HAS_NOR) {
773 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
774 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
776 /* only one device will be jumpered and detected */
778 platform_device_register(&davinci_evm_nandflash_device);
780 if (davinci_aemif_setup(&davinci_evm_nandflash_device))
781 pr_warn("%s: Cannot configure AEMIF\n",
785 evm_leds[7].default_trigger = "nand-disk";
788 pr_warn("WARNING: both NAND and NOR flash are enabled; disable one of them.\n");
790 platform_device_register(&davinci_evm_norflash_device);
793 platform_add_devices(davinci_evm_devices,
794 ARRAY_SIZE(davinci_evm_devices));
797 davinci_setup_mmc(0, &dm6446evm_mmc_config);
799 dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg);
801 davinci_serial_init(dm644x_serial_device);
804 /* irlml6401 switches over 1A, in under 8 msec */
805 davinci_setup_usb(1000, 8);
807 if (IS_BUILTIN(CONFIG_PHYLIB)) {
808 soc_info->emac_pdata->phy_id = DM644X_EVM_PHY_ID;
809 /* Register the fixup for PHY on DaVinci */
810 phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
815 MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
816 /* Maintainer: MontaVista Software <source@mvista.com> */
817 .atag_offset = 0x100,
818 .map_io = davinci_evm_map_io,
819 .init_irq = davinci_irq_init,
820 .init_time = davinci_timer_init,
821 .init_machine = davinci_evm_init,
822 .init_late = davinci_init_late,
823 .dma_zone_size = SZ_128M,
824 .restart = davinci_restart,