1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
10 - Minda Chen <minda.chen@starfivetech.com>
14 const: starfive,jh7110-usb
19 $ref: /schemas/types.yaml#/definitions/phandle-array
22 - description: phandle to System Register Controller stg_syscon node.
23 - description: dr mode register offset of STG_SYSCONSAIF__SYSCFG register for USB.
25 The phandle to System Register Controller syscon node and the offset
26 of STG_SYSCONSAIF__SYSCFG register for USB.
29 enum: [host, otg, peripheral]
39 - description: link power management clock
40 - description: standby clock
41 - description: APB clock
42 - description: AXI clock
43 - description: UTMI APB clock
55 - description: Power up reset
56 - description: APB clock reset
57 - description: AXI clock reset
58 - description: UTMI APB clock reset
70 description: Required child node
82 additionalProperties: false
87 compatible = "starfive,jh7110-usb";
88 ranges = <0x0 0x10100000 0x100000>;
91 starfive,stg-syscon = <&stg_syscon 0x4>;
97 clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
98 resets = <&stgcrg 10>,
102 reset-names = "pwrup", "apb", "axi", "utmi_apb";
106 compatible = "cdns,usb3";
110 reg-names = "otg", "xhci", "dev";
111 interrupts = <100>, <108>, <110>;
112 interrupt-names = "host", "peripheral", "otg";
113 maximum-speed = "super-speed";