1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3399 SuperSpeed DWC3 USB SoC controller
10 - Heiko Stuebner <heiko@sntech.de>
14 const: rockchip,rk3399-dwc3
27 Controller reference clock, must to be 24 MHz
29 Controller suspend clock, must to be 24 MHz or 32 KHz
31 Master/Core clock, must to be >= 62.5 MHz for SS
32 operation and >= 30MHz for HS operation
45 - const: aclk_usb3_rksoc_axi_perf
59 additionalProperties: false
73 #include <dt-bindings/clock/rk3399-cru.h>
74 #include <dt-bindings/power/rk3399-power.h>
75 #include <dt-bindings/interrupt-controller/arm-gic.h>
82 compatible = "rockchip,rk3399-dwc3";
86 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
87 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
88 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
89 clock-names = "ref_clk", "suspend_clk",
90 "bus_clk", "aclk_usb3_rksoc_axi_perf",
91 "aclk_usb3", "grf_clk";
92 resets = <&cru SRST_A_USB3_OTG0>;
93 reset-names = "usb3-otg";
96 compatible = "snps,dwc3";
97 reg = <0x0 0xfe800000 0x0 0x100000>;
98 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
99 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
100 <&cru SCLK_USB3OTG0_SUSPEND>;
101 clock-names = "ref", "bus_early", "suspend";
103 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
104 phy-names = "usb2-phy", "usb3-phy";
105 phy_type = "utmi_wide";
106 snps,dis_enblslpm_quirk;
107 snps,dis-u2-freeclk-exists-quirk;
108 snps,dis_u2_susphy_quirk;
109 snps,dis-del-phy-power-chg-quirk;
110 snps,dis-tx-ipgap-linecheck-quirk;
111 power-domains = <&power RK3399_PD_USB3>;