1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SuperSpeed DWC3 USB SoC controller
10 - Heiko Stuebner <heiko@sntech.de>
13 The common content of the node is defined in snps,dwc3.yaml.
15 Phy documentation is provided in the following places.
18 Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
21 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
28 - rockchip,rk3328-dwc3
29 - rockchip,rk3568-dwc3
30 - rockchip,rk3588-dwc3
38 - rockchip,rk3328-dwc3
39 - rockchip,rk3568-dwc3
40 - rockchip,rk3588-dwc3
53 Controller reference clock, must to be 24 MHz
55 Controller suspend clock, must to be 24 MHz or 32 KHz
57 Master/Core clock, must to be >= 62.5 MHz for SS
58 operation and >= 30MHz for HS operation
60 Controller grf clock OR UTMI clock
84 unevaluatedProperties: false
94 - $ref: snps,dwc3.yaml#
99 const: rockchip,rk3328-dwc3
116 const: rockchip,rk3568-dwc3
127 const: rockchip,rk3588-dwc3
141 #include <dt-bindings/clock/rk3328-cru.h>
142 #include <dt-bindings/interrupt-controller/arm-gic.h>
145 #address-cells = <2>;
148 usbdrd3_0: usb@fe800000 {
149 compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
150 reg = <0x0 0xfe800000 0x0 0x100000>;
151 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
154 clock-names = "ref_clk", "suspend_clk",
155 "bus_clk", "grf_clk";