1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra186-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 xHCI controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
14 exposed by the Tegra XUSB pad controller.
18 const: nvidia,tegra186-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
32 - description: xHCI host interrupt
33 - description: mailbox interrupt
37 - description: XUSB host clock
38 - description: XUSB Falcon source clock
39 - description: XUSB SuperSpeed clock
40 - description: XUSB SuperSpeed source clock
41 - description: XUSB HighSpeed clock source
42 - description: XUSB FullSpeed clock source
43 - description: USB PLL
44 - description: reference clock
45 - description: I/O PLL
50 - const: xusb_falcon_src
61 - description: read client
62 - description: write client
66 - const: dma-mem # read
73 $ref: /schemas/types.yaml#/definitions/phandle
74 description: phandle to the XUSB pad controller that is used to configure
75 the USB pads used by the XHCI controller
96 - description: XUSBC power domain (for Host and USB 2.0)
97 - description: XUSBA power domain (for SuperSpeed)
105 description: PCIe/USB3 analog logic power supply. Must supply 1.05 V.
108 description: High-voltage PCIe/USB3 power supply. Must supply 1.8 V.
111 description: USB controller power supply. Must supply 3.3 V.
113 avdd-pll-utmip-supply:
114 description: UTMI PLL power supply. Must supply 1.8 V.
116 avdd-pll-uerefe-supply:
117 description: PLLE reference PLL power supply. Must supply 1.05 V.
119 dvdd-usb-ss-pll-supply:
120 description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
122 hvdd-usb-ss-pll-e-supply:
123 description: High-voltage PLLE power supply. Must supply 1.8 V.
126 - $ref: usb-xhci.yaml
128 unevaluatedProperties: false
132 #include <dt-bindings/clock/tegra186-clock.h>
133 #include <dt-bindings/interrupt-controller/arm-gic.h>
134 #include <dt-bindings/memory/tegra186-mc.h>
135 #include <dt-bindings/power/tegra186-powergate.h>
136 #include <dt-bindings/reset/tegra186-reset.h>
139 compatible = "nvidia,tegra186-xusb";
140 reg = <0x03530000 0x8000>,
142 reg-names = "hcd", "fpci";
143 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
146 <&bpmp TEGRA186_CLK_XUSB_FALCON>,
147 <&bpmp TEGRA186_CLK_XUSB_SS>,
148 <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
149 <&bpmp TEGRA186_CLK_CLK_M>,
150 <&bpmp TEGRA186_CLK_XUSB_FS>,
151 <&bpmp TEGRA186_CLK_PLLU>,
152 <&bpmp TEGRA186_CLK_CLK_M>,
153 <&bpmp TEGRA186_CLK_PLLE>;
154 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
155 "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
156 "pll_u_480m", "clk_m", "pll_e";
157 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
158 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
159 power-domain-names = "xusb_host", "xusb_ss";
160 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>,
161 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>;
162 interconnect-names = "dma-mem", "write";
163 iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
164 nvidia,xusb-padctl = <&padctl>;
166 #address-cells = <1>;
169 phys = <&phy_usb2_0>, <&phy_usb2_1>, <&phy_usb3_0>;
170 phy-names = "usb2-0", "usb2-1", "usb3-0";