1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - xlnx,versal-qspi-1.0
19 - xlnx,zynqmp-qspi-1.0
48 unevaluatedProperties: false
52 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
58 compatible = "xlnx,zynqmp-qspi-1.0";
59 clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
60 clock-names = "ref_clk", "pclk";
61 interrupts = <0 15 4>;
62 interrupt-parent = <&gic>;
63 reg = <0x0 0xff0f0000 0x0 0x1000>,
64 <0x0 0xc0000000 0x0 0x8000000>;