1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Quad Serial Peripheral Interface (QSPI)
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 description: The QSPI controller allows SPI protocol communication in single,
13 dual, or quad wire transmission modes for read/write access to slaves such
17 - $ref: /schemas/spi/spi-controller.yaml#
45 - description: AHB clock
46 - description: QSPI core clock
58 operating-points-v2: true
70 unevaluatedProperties: false
74 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
75 #include <dt-bindings/interrupt-controller/arm-gic.h>
82 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
83 reg = <0 0x88df000 0 0x600>;
86 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
87 clock-names = "iface", "core";
88 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
89 <&gcc GCC_QSPI_CORE_CLK>;
92 compatible = "jedec,spi-nor";
94 spi-max-frequency = <25000000>;
95 spi-tx-bus-width = <2>;
96 spi-rx-bus-width = <2>;