1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra20-slink.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20/30 SLINK controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-slink
17 - nvidia,tegra30-slink
27 - description: module clock
31 - description: module reset
39 - description: DMA channel used for reception
40 - description: DMA channel used for transmission
48 $ref: /schemas/types.yaml#/definitions/phandle
52 - description: phandle to the core power domain
55 description: Maximum SPI clocking speed of the controller in Hz.
56 $ref: /schemas/types.yaml#/definitions/uint32
59 - $ref: spi-controller.yaml
61 unevaluatedProperties: false
75 #include <dt-bindings/clock/tegra20-car.h>
76 #include <dt-bindings/interrupt-controller/arm-gic.h>
79 compatible = "nvidia,tegra20-slink";
80 reg = <0x7000d600 0x200>;
81 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
82 spi-max-frequency = <25000000>;
85 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
86 resets = <&tegra_car 44>;
88 dmas = <&apbdma 16>, <&apbdma 16>;
89 dma-names = "rx", "tx";