bindings/pinctrl/xlnx,zynq-pinctrl.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/xlnx,zynq-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Xilinx Zynq Pinctrl
   8
   9 maintainers:
  10   - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
  11
  12 description: |
  13   Please refer to pinctrl-bindings.txt in this directory for details of the
  14   common pinctrl bindings used by client devices, including the meaning of the
  15   phrase "pin configuration node".
  16
  17   Zynq's pin configuration nodes act as a container for an arbitrary number of
  18   subnodes. Each of these subnodes represents some desired configuration for a
  19   pin, a group, or a list of pins or groups. This configuration can include the
  20   mux function to select on those pin(s)/group(s), and various pin configuration
  21   parameters, such as pull-up, slew rate, etc.
  22
  23   Each configuration node can consist of multiple nodes describing the pinmux and
  24   pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
  25
  26   The name of each subnode is not important; all subnodes should be enumerated
  27   and processed purely based on their content.
  28
  29 properties:
  30   compatible:
  31     const: xlnx,zynq-pinctrl
  32
  33   reg:
  34     description: Specifies the base address and size of the SLCR space.
  35     maxItems: 1
  36
  37   syscon:
  38     description:
  39       phandle to the SLCR.
  40
  41 patternProperties:
  42   '^(.*-)?(default|gpio-grp)$':
  43     type: object
  44     patternProperties:
  45       '^mux':
  46         type: object
  47         description:
  48           Pinctrl node's client devices use subnodes for pin muxes,
  49           which in turn use below standard properties.
  50         $ref: pinmux-node.yaml#
  51
  52         properties:
  53           groups:
  54             description:
  55               List of groups to select (either this or "pins" must be
  56               specified), available groups for this subnode.
  57             items:
  58               enum: [ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp,
  59                      mdio1_0_grp, qspi0_0_grp, qspi1_0_grp, qspi_fbclk,
  60                      qspi_cs1_grp, spi0_0_grp, spi0_1_grp, spi0_2_grp,
  61                      spi0_0_ss0, spi0_0_ss1, spi0_0_ss2, spi0_1_ss0,
  62                      spi0_1_ss1, spi0_1_ss2, spi0_2_ss0, spi0_2_ss1,
  63                      spi0_2_ss2, spi1_0_grp, spi1_1_grp, spi1_2_grp,
  64                      spi1_3_grp, spi1_0_ss0, spi1_0_ss1, spi1_0_ss2,
  65                      spi1_1_ss0, spi1_1_ss1, spi1_1_ss2, spi1_2_ss0,
  66                      spi1_2_ss1, spi1_2_ss2, spi1_3_ss0, spi1_3_ss1,
  67                      spi1_3_ss2, sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
  68                      sdio1_0_grp, sdio1_1_grp, sdio1_2_grp, sdio1_3_grp,
  69                      sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp,
  70                      sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp,
  71                      smc0_nor_addr25_grp, smc0_nand, can0_0_grp, can0_1_grp,
  72                      can0_2_grp, can0_3_grp, can0_4_grp, can0_5_grp,
  73                      can0_6_grp, can0_7_grp, can0_8_grp, can0_9_grp,
  74                      can0_10_grp, can1_0_grp, can1_1_grp, can1_2_grp,
  75                      can1_3_grp, can1_4_grp, can1_5_grp, can1_6_grp,
  76                      can1_7_grp, can1_8_grp, can1_9_grp, can1_10_grp,
  77                      can1_11_grp, uart0_0_grp, uart0_1_grp, uart0_2_grp,
  78                      uart0_3_grp, uart0_4_grp, uart0_5_grp, uart0_6_grp,
  79                      uart0_7_grp, uart0_8_grp, uart0_9_grp, uart0_10_grp,
  80                      uart1_0_grp, uart1_1_grp, uart1_2_grp, uart1_3_grp,
  81                      uart1_4_grp, uart1_5_grp, uart1_6_grp, uart1_7_grp,
  82                      uart1_8_grp, uart1_9_grp, uart1_10_grp, uart1_11_grp,
  83                      i2c0_0_grp, i2c0_1_grp, i2c0_2_grp, i2c0_3_grp,
  84                      i2c0_4_grp, i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
  85                      i2c0_8_grp, i2c0_9_grp, i2c0_10_grp, i2c1_0_grp,
  86                      i2c1_1_grp, i2c1_2_grp, i2c1_3_grp, i2c1_4_grp,
  87                      i2c1_5_grp, i2c1_6_grp, i2c1_7_grp, i2c1_8_grp,
  88                      i2c1_9_grp, i2c1_10_grp, ttc0_0_grp, ttc0_1_grp,
  89                      ttc0_2_grp, ttc1_0_grp, ttc1_1_grp, ttc1_2_grp,
  90                      swdt0_0_grp, swdt0_1_grp, swdt0_2_grp, swdt0_3_grp,
  91                      swdt0_4_grp, gpio0_0_grp, gpio0_1_grp, gpio0_2_grp,
  92                      gpio0_3_grp, gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
  93                      gpio0_7_grp, gpio0_8_grp, gpio0_9_grp, gpio0_10_grp,
  94                      gpio0_11_grp, gpio0_12_grp, gpio0_13_grp, gpio0_14_grp,
  95                      gpio0_15_grp, gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
  96                      gpio0_19_grp, gpio0_20_grp, gpio0_21_grp, gpio0_22_grp,
  97                      gpio0_23_grp, gpio0_24_grp, gpio0_25_grp, gpio0_26_grp,
  98                      gpio0_27_grp, gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
  99                      gpio0_31_grp, gpio0_32_grp, gpio0_33_grp, gpio0_34_grp,
 100                      gpio0_35_grp, gpio0_36_grp, gpio0_37_grp, gpio0_38_grp,
 101                      gpio0_39_grp, gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
 102                      gpio0_43_grp, gpio0_44_grp, gpio0_45_grp, gpio0_46_grp,
 103                      gpio0_47_grp, gpio0_48_grp, gpio0_49_grp, gpio0_50_grp,
 104                      gpio0_51_grp, gpio0_52_grp, gpio0_53_grp, usb0_0_grp,
 105                      usb1_0_grp]
 106             maxItems: 54
 107
 108           function:
 109             description:
 110               Specify the alternative function to be configured for the
 111               given pin groups.
 112             enum: [ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk,
 113                    qspi_cs1, spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc,
 114                    sdio0_cd, sdio0_wp, sdio1, sdio1_pc, sdio1_cd, sdio1_wp,
 115                    smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0,
 116                    can1, uart0, uart1, i2c0, i2c1, ttc0, ttc1, swdt0, gpio0,
 117                    usb0, usb1]
 118
 119         required:
 120           - groups
 121           - function
 122
 123         additionalProperties: false
 124
 125       '^conf':
 126         type: object
 127         description:
 128           Pinctrl node's client devices use subnodes for pin configurations,
 129           which in turn use the standard properties below.
 130         $ref: pincfg-node.yaml#
 131
 132         properties:
 133           groups:
 134             description:
 135               List of pin groups as mentioned above.
 136
 137           pins:
 138             description:
 139               List of pin names to select in this subnode.
 140             items:
 141               pattern: '^MIO([0-9]|[1-4][0-9]|5[0-3])$'
 142             maxItems: 54
 143
 144           bias-pull-up: true
 145
 146           bias-pull-down: true
 147
 148           bias-disable: true
 149
 150           bias-high-impedance: true
 151
 152           low-power-enable: true
 153
 154           low-power-disable: true
 155
 156           slew-rate:
 157             enum: [0, 1]
 158
 159           power-source:
 160             enum: [1, 2, 3, 4]
 161
 162         oneOf:
 163           - required: [ groups ]
 164           - required: [ pins ]
 165
 166         additionalProperties: false
 167
 168     additionalProperties: false
 169
 170 allOf:
 171   - $ref: pinctrl.yaml#
 172
 173 required:
 174   - compatible
 175   - reg
 176   - syscon
 177
 178 additionalProperties: false
 179
 180 examples:
 181   - |
 182     #include <dt-bindings/pinctrl/pinctrl-zynq.h>
 183     pinctrl0: pinctrl@700 {
 184        compatible = "xlnx,zynq-pinctrl";
 185        reg = <0x700 0x200>;
 186        syscon = <&slcr>;
 187
 188        pinctrl_uart1_default: uart1-default {
 189            mux {
 190                groups = "uart1_10_grp";
 191                function = "uart1";
 192            };
 193
 194            conf {
 195                groups = "uart1_10_grp";
 196                slew-rate = <0>;
 197                power-source = <IO_STANDARD_LVCMOS18>;
 198            };
 199
 200            conf-rx {
 201                pins = "MIO49";
 202                bias-high-impedance;
 203            };
 204
 205            conf-tx {
 206                pins = "MIO48";
 207                bias-disable;
 208            };
 209        };
 210     };
 211
 212     uart1 {
 213          pinctrl-names = "default";
 214          pinctrl-0 = <&pinctrl_uart1_default>;
 215     };
 216
 217 ...