bindings/pinctrl/qcom,x1e80100-tlmm.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,x1e80100-tlmm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. X1E80100 TLMM block
   8
   9 maintainers:
  10   - Rajendra Nayak <quic_rjendra@quicinc.com>
  11
  12 description:
  13   Top Level Mode Multiplexer pin controller in Qualcomm X1E80100 SoC.
  14
  15 allOf:
  16   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
  17
  18 properties:
  19   compatible:
  20     const: qcom,x1e80100-tlmm
  21
  22   reg:
  23     maxItems: 1
  24
  25   interrupts:
  26     maxItems: 1
  27
  28   gpio-reserved-ranges:
  29     minItems: 1
  30     maxItems: 119
  31
  32   gpio-line-names:
  33     maxItems: 238
  34
  35 patternProperties:
  36   "-state$":
  37     oneOf:
  38       - $ref: "#/$defs/qcom-x1e80100-tlmm-state"
  39       - patternProperties:
  40           "-pins$":
  41             $ref: "#/$defs/qcom-x1e80100-tlmm-state"
  42         additionalProperties: false
  43
  44 $defs:
  45   qcom-x1e80100-tlmm-state:
  46     type: object
  47     description:
  48       Pinctrl node's client devices use subnodes for desired pin configuration.
  49       Client device subnodes use below standard properties.
  50     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  51     unevaluatedProperties: false
  52
  53     properties:
  54       pins:
  55         description:
  56           List of gpio pins affected by the properties specified in this
  57           subnode.
  58         items:
  59           oneOf:
  60             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-2][0-9]|23[0-7])$"
  61             - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
  62         minItems: 1
  63         maxItems: 36
  64
  65       function:
  66         description:
  67           Specify the alternative function to be configured for the specified
  68           pins.
  69         enum: [ aon_cci, aoss_cti, atest_char, atest_char0,
  70                 atest_char1, atest_char2, atest_char3, atest_usb,
  71                 audio_ext, audio_ref, cam_aon, cam_mclk, cci_async,
  72                 cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3,
  73                 cci_timer4, cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3,
  74                 cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
  75                 ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, ddr_pxi6, ddr_pxi7,
  76                 edp0_hot, edp0_lcd, edp1_hot, edp1_lcd, eusb0_ac, eusb1_ac,
  77                 eusb2_ac, eusb3_ac, eusb5_ac, eusb6_ac, gcc_gp1, gcc_gp2,
  78                 gcc_gp3, gpio, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, i2s1_data0,
  79                 i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c, jitter_bist, mdp_vsync0,
  80                 mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5,
  81                 mdp_vsync6, mdp_vsync7, mdp_vsync8, pcie3_clk, pcie4_clk,
  82                 pcie5_clk, pcie6a_clk, pcie6b_clk, phase_flag, pll_bist, pll_clk,
  83                 prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
  84                 qdss_gpio, qspi00, qspi01, qspi02, qspi03, qspi0_clk, qspi0_cs0,
  85                 qspi0_cs1, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4,
  86                 qup0_se5, qup0_se6, qup0_se7, qup1_se0, qup1_se1, qup1_se2, qup1_se3,
  87                 qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, qup2_se2,
  88                 qup2_se3, qup2_se4, qup2_se5, qup2_se6, qup2_se7, sd_write, sdc4_clk,
  89                 sdc4_cmd, sdc4_data0, sdc4_data1, sdc4_data2, sdc4_data3, sys_throttle,
  90                 tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tgu_ch4, tgu_ch5,
  91                 tgu_ch6, tgu_ch7, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
  92                 tsense_pwm1, tsense_pwm2, sense_pwm3, tsense_pwm4, usb0_dp, usb0_phy,
  93                 usb0_sbrx, usb0_sbtx, usb1_dp, usb1_phy, usb1_sbrx, usb1_sbtx,
  94                 usb2_dp, usb2_phy, usb2_sbrx, usb2_sbtx, vsense_trigger ]
  95
  96     required:
  97       - pins
  98
  99 required:
 100   - compatible
 101   - reg
 102
 103 unevaluatedProperties: false
 104
 105 examples:
 106   - |
 107     #include <dt-bindings/interrupt-controller/arm-gic.h>
 108     tlmm: pinctrl@f100000 {
 109         compatible = "qcom,x1e80100-tlmm";
 110         reg = <0x0f100000 0xf00000>;
 111         gpio-controller;
 112         #gpio-cells = <2>;
 113         gpio-ranges = <&tlmm 0 0 239>;
 114         interrupt-controller;
 115         #interrupt-cells = <2>;
 116         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 117
 118         gpio-wo-state {
 119             pins = "gpio1";
 120             function = "gpio";
 121         };
 122
 123         uart-w-state {
 124             rx-pins {
 125                 pins = "gpio26";
 126                 function = "qup2_se7";
 127                 bias-pull-up;
 128             };
 129
 130             tx-pins {
 131                 pins = "gpio27";
 132                 function = "qup2_se7";
 133                 bias-disable;
 134             };
 135         };
 136     };
 137 ...