bindings/pinctrl/qcom,sm8650-tlmm.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8650-tlmm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. SM8650 TLMM block
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11
  12 description:
  13   Top Level Mode Multiplexer pin controller in Qualcomm SM8650 SoC.
  14
  15 allOf:
  16   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
  17
  18 properties:
  19   compatible:
  20     const: qcom,sm8650-tlmm
  21
  22   reg:
  23     maxItems: 1
  24
  25   interrupts:
  26     maxItems: 1
  27
  28   gpio-reserved-ranges:
  29     minItems: 1
  30     maxItems: 105
  31
  32   gpio-line-names:
  33     maxItems: 210
  34
  35 patternProperties:
  36   "-state$":
  37     oneOf:
  38       - $ref: "#/$defs/qcom-sm8650-tlmm-state"
  39       - patternProperties:
  40           "-pins$":
  41             $ref: "#/$defs/qcom-sm8650-tlmm-state"
  42         additionalProperties: false
  43
  44 $defs:
  45   qcom-sm8650-tlmm-state:
  46     type: object
  47     description:
  48       Pinctrl node's client devices use subnodes for desired pin configuration.
  49       Client device subnodes use below standard properties.
  50     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  51     unevaluatedProperties: false
  52
  53     properties:
  54       pins:
  55         description:
  56           List of gpio pins affected by the properties specified in this
  57           subnode.
  58         items:
  59           oneOf:
  60             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
  61             - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
  62         minItems: 1
  63         maxItems: 36
  64
  65       function:
  66         description:
  67           Specify the alternative function to be configured for the specified
  68           pins.
  69         enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0,
  70                 audio_ext_mclk1, audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4,
  71                 cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer,
  72                 cmu_rng, coex_uart1_rx, coex_uart1_tx, coex_uart2_rx,
  73                 coex_uart2_tx, cri_trng, dbg_out_clk, ddr_bist_complete,
  74                 ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi0,
  75                 ddr_pxi1, ddr_pxi2, ddr_pxi3, do_not, dp_hot, gcc_gp1,
  76                 gcc_gp2, gcc_gp3, gnss_adc0, gnss_adc1, i2chub0_se0,
  77                 i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4,
  78                 i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8,
  79                 i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws,
  80                 i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c,
  81                 jitter_bist, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out,
  82                 mdp_vsync2_out, mdp_vsync3_out, mdp_vsync_e, nav_gpio0,
  83                 nav_gpio1, nav_gpio2, nav_gpio3, pcie0_clk_req_n,
  84                 pcie1_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux,
  85                 prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
  86                 qdss_gpio, qlink_big_enable, qlink_big_request,
  87                 qlink_little_enable, qlink_little_request, qlink_wmss,
  88                 qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup1_se0,
  89                 qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5, qup1_se6,
  90                 qup1_se7, qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4,
  91                 qup2_se5, qup2_se6, qup2_se7, sd_write_protect, sdc40, sdc41,
  92                 sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4,
  93                 tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout,
  94                 tgu_ch3_trigout, tmess_prng0, tmess_prng1, tmess_prng2,
  95                 tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, uim0_clk,
  96                 uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data,
  97                 uim1_present, uim1_reset, usb1_hs, usb_phy, vfr_0, vfr_1,
  98                 vsense_trigger_mirnat ]
  99
 100     required:
 101       - pins
 102
 103 required:
 104   - compatible
 105   - reg
 106
 107 unevaluatedProperties: false
 108
 109 examples:
 110   - |
 111     #include <dt-bindings/interrupt-controller/arm-gic.h>
 112     tlmm: pinctrl@f100000 {
 113         compatible = "qcom,sm8650-tlmm";
 114         reg = <0x0f100000 0x300000>;
 115         gpio-controller;
 116         #gpio-cells = <2>;
 117         gpio-ranges = <&tlmm 0 0 211>;
 118         interrupt-controller;
 119         #interrupt-cells = <2>;
 120         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 121
 122         gpio-wo-state {
 123             pins = "gpio1";
 124             function = "gpio";
 125         };
 126
 127         uart-w-state {
 128             rx-pins {
 129                 pins = "gpio60";
 130                 function = "qup1_se7";
 131                 bias-pull-up;
 132             };
 133
 134             tx-pins {
 135                 pins = "gpio61";
 136                 function = "qup1_se7";
 137                 bias-disable;
 138             };
 139         };
 140     };
 141 ...