bindings/pinctrl/qcom,sm8450-tlmm.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-tlmm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. SM8450 TLMM block
   8
   9 maintainers:
  10   - Vinod Koul <vkoul@kernel.org>
  11
  12 description:
  13   Top Level Mode Multiplexer pin controller in Qualcomm SM8450 SoC.
  14
  15 allOf:
  16   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
  17
  18 properties:
  19   compatible:
  20     const: qcom,sm8450-tlmm
  21
  22   reg:
  23     maxItems: 1
  24
  25   interrupts:
  26     maxItems: 1
  27
  28   gpio-reserved-ranges:
  29     minItems: 1
  30     maxItems: 105
  31
  32   gpio-line-names:
  33     maxItems: 210
  34
  35 patternProperties:
  36   "-state$":
  37     oneOf:
  38       - $ref: "#/$defs/qcom-sm8450-tlmm-state"
  39       - patternProperties:
  40           "-pins$":
  41             $ref: "#/$defs/qcom-sm8450-tlmm-state"
  42         additionalProperties: false
  43
  44 $defs:
  45   qcom-sm8450-tlmm-state:
  46     type: object
  47     description:
  48       Pinctrl node's client devices use subnodes for desired pin configuration.
  49       Client device subnodes use below standard properties.
  50     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  51     unevaluatedProperties: false
  52
  53     properties:
  54       pins:
  55         description:
  56           List of gpio pins affected by the properties specified in this
  57           subnode.
  58         items:
  59           oneOf:
  60             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
  61             - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
  62         minItems: 1
  63         maxItems: 36
  64
  65       function:
  66         description:
  67           Specify the alternative function to be configured for the specified
  68           pins.
  69         enum: [ aon_cam, atest_char, atest_usb, audio_ref, cam_mclk, cci_async,
  70                 cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng,
  71                 cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
  72                 ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1, gcc_gp2, gcc_gp3,
  73                 gpio, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1,
  74                 mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck,
  75                 mi2s0_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws,
  76                 mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
  77                 mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6,
  78                 mss_grfc7, mss_grfc8, mss_grfc9, nav, pcie0_clkreqn,
  79                 pcie1_clkreqn, phase_flag, pll_bist, pll_clk, pri_mi2s,
  80                 prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, qlink0_request,
  81                 qlink0_wmss, qlink1_enable, qlink1_request, qlink1_wmss,
  82                 qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1,
  83                 qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11,
  84                 qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19, qup2,
  85                 qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4,
  86                 qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk,
  87                 sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2,
  88                 tgu_ch3, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
  89                 tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present,
  90                 uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset,
  91                 usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ]
  92
  93     required:
  94       - pins
  95
  96 required:
  97   - compatible
  98   - reg
  99
 100 unevaluatedProperties: false
 101
 102 examples:
 103   - |
 104     #include <dt-bindings/interrupt-controller/arm-gic.h>
 105     pinctrl@f100000 {
 106         compatible = "qcom,sm8450-tlmm";
 107         reg = <0x0f100000 0x300000>;
 108         gpio-controller;
 109         #gpio-cells = <2>;
 110         gpio-ranges = <&tlmm 0 0 211>;
 111         interrupt-controller;
 112         #interrupt-cells = <2>;
 113         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 114
 115         gpio-wo-state {
 116             pins = "gpio1";
 117             function = "gpio";
 118         };
 119
 120         uart-w-state {
 121             rx-pins {
 122                 pins = "gpio26";
 123                 function = "qup7";
 124                 bias-pull-up;
 125             };
 126
 127             tx-pins {
 128                 pins = "gpio27";
 129                 function = "qup7";
 130                 bias-disable;
 131             };
 132         };
 133     };
 134 ...