bindings/pinctrl/qcom,sdx55-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sdx55-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. SDX55 TLMM block
   8
   9 maintainers:
  10   - Vinod Koul <vkoul@kernel.org>
  11
  12 description:
  13   Top Level Mode Multiplexer pin controller in Qualcomm SDX55 SoC.
  14
  15 properties:
  16   compatible:
  17     const: qcom,sdx55-pinctrl
  18
  19   reg:
  20     description: Specifies the base address and size of the TLMM register space
  21     maxItems: 1
  22
  23   interrupts:
  24     maxItems: 1
  25
  26   gpio-reserved-ranges:
  27     maxItems: 1
  28
  29 patternProperties:
  30   "-state$":
  31     oneOf:
  32       - $ref: "#/$defs/qcom-sdx55-tlmm-state"
  33       - patternProperties:
  34           "-pins$":
  35             $ref: "#/$defs/qcom-sdx55-tlmm-state"
  36         additionalProperties: false
  37
  38 $defs:
  39   qcom-sdx55-tlmm-state:
  40     type: object
  41     description:
  42       Pinctrl node's client devices use subnodes for desired pin configuration.
  43       Client device subnodes use below standard properties.
  44     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  45     unevaluatedProperties: false
  46
  47     properties:
  48       pins:
  49         description:
  50           List of gpio pins affected by the properties specified in this subnode.
  51         items:
  52           oneOf:
  53             - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$"
  54             - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
  55         minItems: 1
  56         maxItems: 36
  57
  58       function:
  59         description:
  60           Specify the alternative function to be configured for the specified
  61           pins. Functions are only valid for gpio pins.
  62         enum: [ adsp_ext, atest, audio_ref, bimc_dte0, bimc_dte1, blsp_i2c1,
  63                 blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_spi1, blsp_spi2,
  64                 blsp_spi3, blsp_spi4, blsp_uart1, blsp_uart2, blsp_uart3,
  65                 blsp_uart4, char_exec, coex_uart, coex_uart2, cri_trng,
  66                 cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
  67                 ebi0_wrcdc, ebi2_a, ebi2_lcd, emac_gcc0, emac_gcc1,
  68                 emac_pps0, emac_pps1, ext_dbg, gcc_gp1, gcc_gp2, gcc_gp3,
  69                 gcc_plltest, gpio, i2s_mclk, jitter_bist, ldo_en, ldo_update,
  70                 mgpi_clk, m_voc, native_char, native_char0, native_char1,
  71                 native_char2, native_char3, native_tsens, native_tsense,
  72                 nav_gpio, pa_indicator, pcie_clkreq, pci_e, pll_bist, pll_ref,
  73                 pll_test, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio,
  74                 qdss_gpio0, qdss_gpio1, qdss_gpio2, qdss_gpio3, qdss_gpio4,
  75                 qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9,
  76                 qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13,
  77                 qdss_gpio14, qdss_gpio15, qdss_stm0, qdss_stm1, qdss_stm2,
  78                 qdss_stm3, qdss_stm4, qdss_stm5, qdss_stm6, qdss_stm7,
  79                 qdss_stm8, qdss_stm9, qdss_stm10, qdss_stm11, qdss_stm12,
  80                 qdss_stm13, qdss_stm14, qdss_stm15, qdss_stm16, qdss_stm17,
  81                 qdss_stm18, qdss_stm19, qdss_stm20, qdss_stm21, qdss_stm22,
  82                 qdss_stm23, qdss_stm24, qdss_stm25, qdss_stm26, qdss_stm27,
  83                 qdss_stm28, qdss_stm29, qdss_stm30, qdss_stm31, qlink0_en,
  84                 qlink0_req, qlink0_wmss, qlink1_en, qlink1_req, qlink1_wmss,
  85                 spmi_coex, sec_mi2s, spmi_vgi, tgu_ch0, uim1_clk, uim1_data,
  86                 uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present,
  87                 uim2_reset, usb2phy_ac, vsense_trigger ]
  88
  89     required:
  90       - pins
  91
  92 allOf:
  93   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
  94
  95 required:
  96   - compatible
  97   - reg
  98
  99 unevaluatedProperties: false
 100
 101 examples:
 102   - |
 103     #include <dt-bindings/interrupt-controller/arm-gic.h>
 104     tlmm: pinctrl@1f00000 {
 105         compatible = "qcom,sdx55-pinctrl";
 106         reg = <0x0f100000 0x300000>;
 107         gpio-controller;
 108         #gpio-cells = <2>;
 109         gpio-ranges = <&tlmm 0 0 108>;
 110         interrupt-controller;
 111         #interrupt-cells = <2>;
 112         interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
 113
 114         serial-state {
 115             pins = "gpio8", "gpio9";
 116             function = "blsp_uart3";
 117             drive-strength = <8>;
 118             bias-disable;
 119         };
 120     };
 121
 122 ...