bindings/pinctrl/qcom,sdm845-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,sdm845-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SDM845 TLMM pin controller
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11   - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  12
  13 description:
  14   Top Level Mode Multiplexer pin controller in Qualcomm SDM845 SoC.
  15
  16 allOf:
  17   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
  18
  19 properties:
  20   compatible:
  21     const: qcom,sdm845-pinctrl
  22
  23   reg:
  24     maxItems: 1
  25
  26   interrupts:
  27     maxItems: 1
  28
  29   gpio-reserved-ranges:
  30     minItems: 1
  31     maxItems: 75
  32
  33   gpio-line-names:
  34     maxItems: 150
  35
  36 patternProperties:
  37   "-state$":
  38     oneOf:
  39       - $ref: "#/$defs/qcom-sdm845-tlmm-state"
  40       - patternProperties:
  41           "-pins$":
  42             $ref: "#/$defs/qcom-sdm845-tlmm-state"
  43         additionalProperties: false
  44
  45   "-hog(-[0-9]+)?$":
  46     required:
  47       - gpio-hog
  48
  49 $defs:
  50   qcom-sdm845-tlmm-state:
  51     type: object
  52     description:
  53       Pinctrl node's client devices use subnodes for desired pin configuration.
  54       Client device subnodes use below standard properties.
  55     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  56     unevaluatedProperties: false
  57
  58     properties:
  59       pins:
  60         description:
  61           List of gpio pins affected by the properties specified in this
  62           subnode.
  63         items:
  64           oneOf:
  65             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
  66             - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
  67         minItems: 1
  68         maxItems: 36
  69
  70       function:
  71         description:
  72           Specify the alternative function to be configured for the specified
  73           pins.
  74         enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2,
  75                 atest_usb1, atest_usb10, atest_usb11, atest_usb12, atest_usb13,
  76                 atest_usb2, atest_usb20, atest_usb21, atest_usb22, atest_usb23,
  77                 audio_ref, btfm_slimbus, cam_mclk, cci_async, cci_i2c,
  78                 cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
  79                 cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
  80                 ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1,
  81                 gcc_gp2, gcc_gp3, gpio, jitter_bist, ldo_en, ldo_update,
  82                 lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
  83                 mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator, pci_e0,
  84                 pci_e1, phase_flag, pll_bist, pll_bypassnl, pll_reset,
  85                 pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti, qlink_enable,
  86                 qlink_request, qspi_clk, qspi_cs, qspi_data, qua_mi2s, qup0,
  87                 qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3,
  88                 qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6,
  89                 sdc4_clk, sdc4_cmd, sdc4_data, sd_write, sec_mi2s, sp_cmu,
  90                 spkr_i2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
  91                 tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en,
  92                 tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en,
  93                 tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
  94                 uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
  95                 uim_batt, usb_phy, vfr_1, vsense_trigger, wlan1_adc0,
  96                 wlan1_adc1, wlan2_adc0, wlan2_adc1]
  97
  98     required:
  99       - pins
 100
 101 required:
 102   - compatible
 103   - reg
 104
 105 unevaluatedProperties: false
 106
 107 examples:
 108   - |
 109     #include <dt-bindings/gpio/gpio.h>
 110     #include <dt-bindings/interrupt-controller/arm-gic.h>
 111
 112     pinctrl@3400000 {
 113         compatible = "qcom,sdm845-pinctrl";
 114         reg = <0x03400000 0xc00000>;
 115         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 116         gpio-controller;
 117         #gpio-cells = <2>;
 118         interrupt-controller;
 119         #interrupt-cells = <2>;
 120         gpio-ranges = <&tlmm 0 0 151>;
 121         wakeup-parent = <&pdc_intc>;
 122
 123         ap-suspend-l-hog {
 124             gpio-hog;
 125             gpios = <126 GPIO_ACTIVE_LOW>;
 126             output-low;
 127         };
 128
 129         cci0-default-state {
 130             pins = "gpio17", "gpio18";
 131             function = "cci_i2c";
 132
 133             bias-pull-up;
 134             drive-strength = <2>;
 135         };
 136
 137         cam0-default-state {
 138             rst-pins {
 139                 pins = "gpio9";
 140                 function = "gpio";
 141
 142                 drive-strength = <16>;
 143                 bias-disable;
 144             };
 145
 146             mclk0-pins {
 147                 pins = "gpio13";
 148                 function = "cam_mclk";
 149
 150                 drive-strength = <16>;
 151                 bias-disable;
 152             };
 153         };
 154     };