bindings/pinctrl/qcom,qcm2290-tlmm.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,qcm2290-tlmm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. QCM2290 TLMM block
   8
   9 maintainers:
  10   - Shawn Guo <shawn.guo@linaro.org>
  11
  12 description:
  13   Top Level Mode Multiplexer pin controller in Qualcomm QCM2290 SoC.
  14
  15 properties:
  16   compatible:
  17     const: qcom,qcm2290-tlmm
  18
  19   reg:
  20     maxItems: 1
  21
  22   interrupts:
  23     maxItems: 1
  24
  25 patternProperties:
  26   "-state$":
  27     oneOf:
  28       - $ref: "#/$defs/qcom-qcm2290-tlmm-state"
  29       - patternProperties:
  30           "-pins$":
  31             $ref: "#/$defs/qcom-qcm2290-tlmm-state"
  32         additionalProperties: false
  33
  34 $defs:
  35   qcom-qcm2290-tlmm-state:
  36     type: object
  37     description:
  38       Pinctrl node's client devices use subnodes for desired pin configuration.
  39       Client device subnodes use below standard properties.
  40     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  41     unevaluatedProperties: false
  42
  43     properties:
  44       pins:
  45         description:
  46           List of gpio pins affected by the properties specified in this
  47           subnode.
  48         items:
  49           oneOf:
  50             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[0-6])$"
  51             - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
  52                       sdc2_clk, sdc2_cmd, sdc2_data ]
  53         minItems: 1
  54         maxItems: 36
  55
  56       function:
  57         description:
  58           Specify the alternative function to be configured for the specified
  59           pins.
  60
  61         enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c,
  62                 cci_timer0, cci_timer1, cci_timer2, cci_timer3, char_exec,
  63                 cri_trng, cri_trng0, cri_trng1, dac_calib, dbg_out, ddr_bist,
  64                 ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2,
  65                 gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx,
  66                 jitter_bist, mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1,
  67                 mpm_pwr, mss_lte, m_voc, nav_gpio, pa_indicator, pbs0, pbs1,
  68                 pbs2, pbs3, pbs4, pbs5, pbs6, pbs7, pbs8, pbs9, pbs10, pbs11,
  69                 pbs12, pbs13, pbs14, pbs15, pbs_out, phase_flag, pll_bist,
  70                 pll_bypassnl, pll_reset, prng_rosc, pwm_0, pwm_1, pwm_2, pwm_3,
  71                 pwm_4, pwm_5, pwm_6, pwm_7, pwm_8, pwm_9, qdss_cti, qdss_gpio,
  72                 qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb, sdc2_tb, sd_write,
  73                 ssbi_wtr1, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm,
  74                 uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk,
  75                 uim2_data, uim2_present, uim2_reset, usb_phy, vfr_1,
  76                 vsense_trigger, wlan1_adc0, wlan1_adc1 ]
  77
  78     required:
  79       - pins
  80
  81 allOf:
  82   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
  83
  84 required:
  85   - compatible
  86   - reg
  87
  88 unevaluatedProperties: false
  89
  90 examples:
  91   - |
  92     #include <dt-bindings/interrupt-controller/arm-gic.h>
  93     tlmm: pinctrl@500000 {
  94         compatible = "qcom,qcm2290-tlmm";
  95         reg = <0x500000 0x300000>;
  96         interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
  97         gpio-controller;
  98         #gpio-cells = <2>;
  99         interrupt-controller;
 100         #interrupt-cells = <2>;
 101         gpio-ranges = <&tlmm 0 0 127>;
 102
 103         sdc2_on_state: sdc2-on-state {
 104             clk-pins {
 105                 pins = "sdc2_clk";
 106                 bias-disable;
 107                 drive-strength = <16>;
 108             };
 109
 110             cmd-pins {
 111                 pins = "sdc2_cmd";
 112                 bias-pull-up;
 113                 drive-strength = <10>;
 114             };
 115
 116             data-pins {
 117                 pins = "sdc2_data";
 118                 bias-pull-up;
 119                 drive-strength = <10>;
 120             };
 121         };
 122     };