1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/qcom,mdm9615-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. MDM9615 TLMM block
10 - Bjorn Andersson <andersson@kernel.org>
12 description: Top Level Mode Multiplexer pin controller in Qualcomm MDM9615 SoC.
14 $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18 const: qcom,mdm9615-pinctrl
29 - $ref: "#/$defs/qcom-mdm9615-pinctrl-state"
32 $ref: "#/$defs/qcom-mdm9615-pinctrl-state"
33 additionalProperties: false
36 qcom-mdm9615-pinctrl-state:
39 Pinctrl node's client devices use subnodes for desired pin configuration.
40 Client device subnodes use below standard properties.
41 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
42 unevaluatedProperties: false
47 List of gpio pins affected by the properties specified in this
50 pattern: "^gpio([0-9]|[1-7][0-9]|8[0-7])$"
56 Specify the alternative function to be configured for the specified
59 enum: [ gpio, gsbi2_i2c, gsbi3, gsbi4, gsbi5_i2c, gsbi5_uart,
60 sdc2, ebi2_lcdc, ps_hold, prim_audio, sec_audio, cdc_mclk, ]
69 unevaluatedProperties: false
73 #include <dt-bindings/interrupt-controller/arm-gic.h>
74 tlmm: pinctrl@1000000 {
75 compatible = "qcom,mdm9615-pinctrl";
76 reg = <0x01000000 0x300000>;
77 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
79 gpio-ranges = <&msmgpio 0 0 88>;
82 #interrupt-cells = <2>;
85 pins = "gpio8", "gpio9", "gpio10", "gpio11";
94 function = "gsbi5_i2c";
101 function = "gsbi5_i2c";
102 drive-strength = <2>;