bindings/pinctrl/qcom,ipq9574-tlmm.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq9574-tlmm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. IPQ9574 TLMM block
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11   - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  12
  13 description:
  14   Top Level Mode Multiplexer pin controller in Qualcomm IPQ9574 SoC.
  15
  16 properties:
  17   compatible:
  18     const: qcom,ipq9574-tlmm
  19
  20   reg:
  21     maxItems: 1
  22
  23   interrupts:
  24     maxItems: 1
  25
  26   gpio-reserved-ranges:
  27     minItems: 1
  28     maxItems: 33
  29
  30   gpio-line-names:
  31     maxItems: 65
  32
  33 patternProperties:
  34   "-state$":
  35     oneOf:
  36       - $ref: "#/$defs/qcom-ipq9574-tlmm-state"
  37       - patternProperties:
  38           "-pins$":
  39             $ref: "#/$defs/qcom-ipq9574-tlmm-state"
  40         additionalProperties: false
  41
  42 $defs:
  43   qcom-ipq9574-tlmm-state:
  44     type: object
  45     description:
  46       Pinctrl node's client devices use subnodes for desired pin configuration.
  47       Client device subnodes use below standard properties.
  48     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  49     unevaluatedProperties: false
  50
  51     properties:
  52       pins:
  53         description:
  54           List of gpio pins affected by the properties specified in this
  55           subnode.
  56         items:
  57           pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$"
  58         minItems: 1
  59         maxItems: 8
  60
  61       function:
  62         description:
  63           Specify the alternative function to be configured for the specified
  64           pins.
  65
  66         enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
  67                 audio_pdm0, audio_pdm1, audio_pri, audio_sec, blsp0_spi, blsp0_uart,
  68                 blsp1_i2c, blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi,
  69                 blsp2_uart, blsp3_i2c, blsp3_spi, blsp3_uart, blsp4_i2c,
  70                 blsp4_spi, blsp4_uart, blsp5_i2c, blsp5_uart, cri_trng0,
  71                 cri_trng1, cri_trng2, cri_trng3, cxc0, cxc1, dbg_out, dwc_ddrphy,
  72                 gcc_plltest, gcc_tlmm, gpio, mac, mdc, mdio, pcie0_clk, pcie0_wake,
  73                 pcie1_clk, pcie1_wake, pcie2_clk, pcie2_wake, pcie3_clk, pcie3_wake,
  74                 prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, pta, pwm,
  75                 qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
  76                 qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
  77                 qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
  78                 qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
  79                 qdss_tracedata_b, qspi_clk, qspi_cs, qspi_data,
  80                 rx0, rx1, sdc_clk, sdc_cmd, sdc_data, sdc_rclk, tsens_max,
  81                 wci20, wci21, wsa_swrm ]
  82
  83     required:
  84       - pins
  85
  86 allOf:
  87   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
  88
  89 required:
  90   - compatible
  91   - reg
  92
  93 unevaluatedProperties: false
  94
  95 examples:
  96   - |
  97     #include <dt-bindings/interrupt-controller/arm-gic.h>
  98     tlmm: pinctrl@1000000 {
  99         compatible = "qcom,ipq9574-tlmm";
 100         reg = <0x01000000 0x300000>;
 101         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 102         gpio-controller;
 103         #gpio-cells = <2>;
 104         interrupt-controller;
 105         #interrupt-cells = <2>;
 106         gpio-ranges = <&tlmm 0 0 65>;
 107
 108         uart2-state {
 109             pins = "gpio34", "gpio35";
 110             function = "blsp2_uart";
 111             drive-strength = <8>;
 112             bias-pull-down;
 113         };
 114     };