bindings/pinctrl/qcom,ipq5332-tlmm.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq5332-tlmm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm IPQ5332 TLMM pin controller
   8
   9 maintainers:
  10   - Bjorn Andersson <andersson@kernel.org>
  11   - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  12
  13 description: |
  14   Top Level Mode Multiplexer pin controller in Qualcomm IPQ5332 SoC.
  15
  16 allOf:
  17   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
  18
  19 properties:
  20   compatible:
  21     const: qcom,ipq5332-tlmm
  22
  23   reg:
  24     maxItems: 1
  25
  26   interrupts:
  27     maxItems: 1
  28
  29   gpio-reserved-ranges:
  30     minItems: 1
  31     maxItems: 27
  32
  33   gpio-line-names:
  34     maxItems: 53
  35
  36 patternProperties:
  37   "-state$":
  38     oneOf:
  39       - $ref: "#/$defs/qcom-ipq5332-tlmm-state"
  40       - patternProperties:
  41           "-pins$":
  42             $ref: "#/$defs/qcom-ipq5332-tlmm-state"
  43         additionalProperties: false
  44
  45 $defs:
  46   qcom-ipq5332-tlmm-state:
  47     type: object
  48     description:
  49       Pinctrl node's client devices use subnodes for desired pin configuration.
  50       Client device subnodes use below standard properties.
  51     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
  52     unevaluatedProperties: false
  53
  54     properties:
  55       pins:
  56         description:
  57           List of gpio pins affected by the properties specified in this
  58           subnode.
  59         items:
  60           pattern: "^gpio([0-9]|[1-4][0-9]|5[0-2])$"
  61         minItems: 1
  62         maxItems: 36
  63
  64       function:
  65         description:
  66           Specify the alternative function to be configured for the specified
  67           pins.
  68
  69         enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
  70                 atest_tic, audio_pri, audio_pri0, audio_pri1, audio_sec,
  71                 audio_sec0, audio_sec1, blsp0_i2c, blsp0_spi, blsp0_uart0,
  72                 blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1,
  73                 blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1,
  74                 blsp2_spi, blsp2_spi0, blsp2_spi1, core_voltage, cri_trng0,
  75                 cri_trng1, cri_trng2, cri_trng3, cxc_clk, cxc_data, dbg_out,
  76                 gcc_plltest, gcc_tlmm, gpio, lock_det, mac0, mac1, mdc0, mdc1,
  77                 mdio0, mdio1, pc, pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake,
  78                 pcie2_clk, pcie2_wake, pll_test, prng_rosc0, prng_rosc1,
  79                 prng_rosc2, prng_rosc3, pta, pwm0, pwm1, pwm2, pwm3,
  80                 qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
  81                 qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
  82                 qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
  83                 qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b,
  84                 qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
  85                 qdss_tracedata_b, qspi_data, qspi_clk, qspi_cs, resout, rx0,
  86                 rx1, sdc_data, sdc_clk, sdc_cmd, tsens_max, wci_txd, wci_rxd,
  87                 wsi_clk, wsi_clk3, wsi_data, wsi_data3, wsis_reset, xfem ]
  88
  89     required:
  90       - pins
  91
  92 required:
  93   - compatible
  94   - reg
  95
  96 unevaluatedProperties: false
  97
  98 examples:
  99   - |
 100     #include <dt-bindings/interrupt-controller/arm-gic.h>
 101
 102     tlmm: pinctrl@1000000 {
 103         compatible = "qcom,ipq5332-tlmm";
 104         reg = <0x01000000 0x300000>;
 105         gpio-controller;
 106         #gpio-cells = <0x2>;
 107         gpio-ranges = <&tlmm 0 0 53>;
 108         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
 109         interrupt-controller;
 110         #interrupt-cells = <0x2>;
 111
 112         serial0-state {
 113             pins = "gpio18", "gpio19";
 114             function = "blsp0_uart0";
 115             drive-strength = <8>;
 116             bias-pull-up;
 117         };
 118     };