1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 $id: http://devicetree.org/schemas/pinctrl/nxp,s32g2-siul2-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: NXP S32G2 pin controller
11 - Ghennadi Procopciuc <Ghennadi.Procopciuc@oss.nxp.com>
12 - Chester Lin <chester62515@gmail.com>
15 S32G2 pinmux is implemented in SIUL2 (System Integration Unit Lite2),
16 whose memory map is split into two regions:
20 Every SIUL2 region has multiple register types, and here only MSCR and
21 IMCR registers need to be revealed for kernel to configure pinmux.
23 Please note that some register indexes are reserved in S32G2, such as
24 MSCR102-MSCR111, MSCR123-MSCR143, IMCR84-IMCR118 and IMCR398-IMCR429.
29 - nxp,s32g2-siul2-pinctrl
33 A list of MSCR/IMCR register regions to be reserved.
34 - MSCR (Multiplexed Signal Configuration Register)
35 An MSCR register can configure the associated pin as either a GPIO pin
36 or a function output pin depends on the selected signal source.
37 - IMCR (Input Multiplexed Signal Configuration Register)
38 An IMCR register can configure the associated pin as function input
39 pin depends on the selected signal source.
41 - description: MSCR registers group 0 in SIUL2_0
42 - description: MSCR registers group 1 in SIUL2_1
43 - description: MSCR registers group 2 in SIUL2_1
44 - description: IMCR registers group 0 in SIUL2_0
45 - description: IMCR registers group 1 in SIUL2_1
46 - description: IMCR registers group 2 in SIUL2_1
51 additionalProperties: false
57 - $ref: pinmux-node.yaml#
58 - $ref: pincfg-node.yaml#
60 Pinctrl node's client devices specify pin muxes using subnodes,
61 which in turn use the standard properties below.
65 bias-high-impedance: true
68 drive-open-drain: true
74 An integer array for representing pinmux configurations of
75 a device. Each integer consists of a PIN_ID and a 4-bit
76 selected signal source(SSS) as IOMUX setting, which is
77 calculated as: pinmux = (PIN_ID << 4 | SSS)
80 description: Supported slew rate based on Fmax values (MHz)
81 enum: [83, 133, 150, 166, 208]
83 additionalProperties: false
89 additionalProperties: false
94 compatible = "nxp,s32g2-siul2-pinctrl";
96 /* MSCR0-MSCR101 registers on siul2_0 */
97 reg = <0x4009c240 0x198>,
98 /* MSCR112-MSCR122 registers on siul2_1 */
100 /* MSCR144-MSCR190 registers on siul2_1 */
102 /* IMCR0-IMCR83 registers on siul2_0 */
104 /* IMCR119-IMCR397 registers on siul2_1 */
106 /* IMCR430-IMCR495 registers on siul2_1 */