bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/nuvoton,npcm845-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Nuvoton NPCM845 Pin Controller and GPIO
   8
   9 maintainers:
  10   - Tomer Maimon <tmaimon77@gmail.com>
  11
  12 description:
  13   The Nuvoton BMC NPCM8XX Pin Controller multi-function routed through
  14   the multiplexing block, Each pin supports GPIO functionality (GPIOx)
  15   and multiple functions that directly connect the pin to different
  16   hardware blocks.
  17
  18 properties:
  19   compatible:
  20     const: nuvoton,npcm845-pinctrl
  21
  22   ranges:
  23     maxItems: 1
  24
  25   '#address-cells':
  26     const: 1
  27
  28   '#size-cells':
  29     const: 1
  30
  31   nuvoton,sysgcr:
  32     $ref: /schemas/types.yaml#/definitions/phandle
  33     description: a phandle to access GCR registers.
  34
  35 patternProperties:
  36   '^gpio@':
  37     type: object
  38     additionalProperties: false
  39
  40     description:
  41       Eight GPIO banks that each contain 32 GPIOs.
  42
  43     properties:
  44       gpio-controller: true
  45
  46       '#gpio-cells':
  47         const: 2
  48
  49       reg:
  50         maxItems: 1
  51
  52       interrupts:
  53         maxItems: 1
  54
  55       gpio-ranges:
  56         maxItems: 1
  57
  58     required:
  59       - gpio-controller
  60       - '#gpio-cells'
  61       - reg
  62       - interrupts
  63       - gpio-ranges
  64
  65   '-mux$':
  66     $ref: pinmux-node.yaml#
  67
  68     properties:
  69       groups:
  70         description:
  71           One or more groups of pins to mux to a certain function
  72         items:
  73           enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,
  74                   smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b,
  75                   smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21,
  76                   smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3,
  77                   spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2,
  78                   spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2,
  79                   bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen,
  80                   r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3,
  81                   fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
  82                   fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,
  83                   pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,
  84                   ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,
  85                   smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
  86                   sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
  87                   mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
  88                   scipme, smi, smb6, smb7, spi1, faninx, r1, spi3, spi3cs1,
  89                   spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den,
  90                   smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix,
  91                   spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
  92                   hgpio5, hgpio6, hgpio7 ]
  93
  94       function:
  95         description:
  96           The function that a group of pins is muxed to
  97         enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,
  98                 smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b,
  99                 smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21,
 100                 smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3,
 101                 spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2,
 102                 spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2,
 103                 bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen,
 104                 r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3,
 105                 fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
 106                 fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,
 107                 pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,
 108                 ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,
 109                 smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
 110                 sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
 111                 mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
 112                 scipme, smi, smb6, smb7, spi1, faninx, r1, spi3, spi3cs1,
 113                 spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den,
 114                 smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix,
 115                 spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
 116                 hgpio5, hgpio6, hgpio7 ]
 117
 118     dependencies:
 119       groups: [ function ]
 120       function: [ groups ]
 121
 122     additionalProperties: false
 123
 124   '^pin':
 125     $ref: pincfg-node.yaml#
 126
 127     properties:
 128       pins:
 129         description:
 130           A list of pins to configure in certain ways, such as enabling
 131           debouncing
 132         items:
 133           pattern: '^GPIO([0-9]|[0-9][0-9]|1[0-9][0-9]|2[0-4][0-9]|25[0-6])'
 134
 135       bias-disable: true
 136
 137       bias-pull-up: true
 138
 139       bias-pull-down: true
 140
 141       input-enable: true
 142
 143       output-low: true
 144
 145       output-high: true
 146
 147       drive-push-pull: true
 148
 149       drive-open-drain: true
 150
 151       input-debounce:
 152         description:
 153           Debouncing periods in microseconds, one period per interrupt
 154           bank found in the controller
 155         $ref: /schemas/types.yaml#/definitions/uint32-array
 156         minItems: 1
 157         maxItems: 4
 158
 159       slew-rate:
 160         description: |
 161           0: Low rate
 162           1: High rate
 163         $ref: /schemas/types.yaml#/definitions/uint32
 164         enum: [0, 1]
 165
 166       drive-strength:
 167         enum: [ 0, 1, 2, 4, 8, 12 ]
 168
 169     additionalProperties: false
 170
 171 allOf:
 172   - $ref: pinctrl.yaml#
 173
 174 required:
 175   - compatible
 176   - ranges
 177   - '#address-cells'
 178   - '#size-cells'
 179   - nuvoton,sysgcr
 180
 181 additionalProperties: false
 182
 183 examples:
 184   - |
 185     #include <dt-bindings/interrupt-controller/arm-gic.h>
 186     #include <dt-bindings/gpio/gpio.h>
 187
 188     soc {
 189       #address-cells = <2>;
 190       #size-cells = <2>;
 191
 192       pinctrl: pinctrl@f0010000 {
 193         compatible = "nuvoton,npcm845-pinctrl";
 194         ranges = <0x0 0x0 0xf0010000 0x8000>;
 195         #address-cells = <1>;
 196         #size-cells = <1>;
 197         nuvoton,sysgcr = <&gcr>;
 198
 199         gpio0: gpio@0 {
 200           gpio-controller;
 201           #gpio-cells = <2>;
 202           reg = <0x0 0xb0>;
 203           interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 204           gpio-ranges = <&pinctrl 0 0 32>;
 205         };
 206
 207         fanin0_pin: fanin0-mux {
 208           groups = "fanin0";
 209           function = "fanin0";
 210         };
 211
 212         pin34_slew: pin34-slew {
 213           pins = "GPIO34/I3C4_SDA";
 214           bias-disable;
 215         };
 216       };
 217     };