1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek MT7986 Pin Controller
10 - Sean Wang <sean.wang@kernel.org>
13 The MediaTek's MT7986 Pin controller is used to control SoC pins.
18 - mediatek,mt7986a-pinctrl
19 - mediatek,mt7986b-pinctrl
41 Number of cells in GPIO specifier. Since the generic GPIO binding is used,
42 the amount of cells must be specified as 2. See the below mentioned gpio
43 binding representation for description of particular cells.
49 GPIO valid number range.
51 interrupt-controller: true
72 additionalProperties: false
77 additionalProperties: false
79 pinmux configuration nodes.
81 The following table shows the effective values of "group", "function"
82 properties and chip pinout pins
84 groups function pins (in pin#)
85 ---------------------------------------------------------------------
86 "watchdog" "watchdog" 0
89 "uart1_0" "uart" 7, 8, 9, 10
90 "uart1_rx_tx" "uart" 42, 43
91 "uart1_cts_rts" "uart" 44, 45
94 "spi1_0" "spi" 11, 12, 13, 14
98 "snfi" "flash" 23, 24, 25, 26, 27, 28
99 "spi1_2" "spi" 29, 30, 31, 32
100 "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
103 "spi1_1" "spi" 23, 24, 25, 26
104 "uart1_2_rx_tx" "uart" 29, 30
105 "uart1_2_cts_rts" "uart" 31, 32
106 "uart1_1" "uart" 23, 24, 25, 26
107 "uart2_0_rx_tx" "uart" 29, 30
108 "uart2_0_cts_rts" "uart" 31, 32
109 "spi0" "spi" 33, 34, 35, 36
110 "spi0_wp_hold" "spi" 37, 38
111 "uart1_3_rx_tx" "uart" 35, 36
112 "uart1_3_cts_rts" "uart" 37, 38
113 "uart2_1" "uart" 33, 34, 35, 36
114 "spi1_3" "spi" 33, 34, 35, 36
115 "uart0" "uart" 39, 40
116 "pcie_pereset" "pcie" 41
117 "uart1" "uart" 42, 43, 44, 45
118 "uart2" "uart" 46, 47, 48, 49
119 "emmc_51" "emmc" 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
122 "pcm" "audio" 62, 63, 64, 65
123 "i2s" "audio" 62, 63, 64, 65
124 "switch_int" "eth" 66
126 "wf_2g" "wifi" 74, 75, 76, 77, 78, 79, 80, 81, 82, 83
127 "wf_5g" "wifi" 91, 92, 93, 94, 95, 96, 97, 98, 99, 100
128 "wf_dbdc" "wifi" 74, 75, 76, 77, 78, 79, 80, 81, 82, 83,
131 $ref: /schemas/pinctrl/pinmux-node.yaml
135 A string containing the name of the function to mux to the group.
136 There is no "audio", "pcie" functions on mt7986b, you can only use
137 those functions on mt7986a.
138 enum: [audio, emmc, eth, i2c, led, flash, pcie, pwm, spi, uart,
142 An array of strings. Each string contains the name of a group.
143 There is no "pcie_pereset", "uart1", "uart2" "emmc_51", "pcm", and
144 "i2s" groups on mt7986b, you can only use those groups on mt7986a.
165 enum: [emmc_45, emmc_51]
173 enum: [switch_int, mdc_mdio]
206 enum: [pcie_clk, pcie_wake, pcie_pereset]
216 enum: [pwm0, pwm1_0, pwm1_1]
226 enum: [spi0, spi0_wp_hold, spi1_0, spi1_1, spi1_2, spi1_3]
236 enum: [uart1_0, uart1_rx_tx, uart1_cts_rts, uart1_1,
237 uart1_2_rx_tx, uart1_2_cts_rts, uart1_3_rx_tx,
238 uart1_3_cts_rts, uart2_0_rx_tx, uart2_0_cts_rts,
239 uart2_1, uart0, uart1, uart2]
257 enum: [wf_2g, wf_5g, wf_dbdc]
261 additionalProperties: false
263 pinconf configuration nodes.
264 $ref: /schemas/pinctrl/pincfg-node.yaml
269 An array of strings. Each string contains the name of a pin. There
270 is no PIN 41 to PIN 65 above on mt7686b, you can only use those
273 enum: [SYS_WATCHDOG, WF2G_LED, WF5G_LED, I2C_SCL, I2C_SDA, GPIO_0,
274 GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7,
275 GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13,
276 GPIO_14, GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI,
277 SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK,
278 SPI1_MOSI, SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI,
279 SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, UART0_RXD,
280 UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART1_TXD, UART1_CTS,
281 UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS, UART2_RTS,
282 EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2, EMMC_DATA_3,
283 EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6, EMMC_DATA_7,
284 EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, PCM_DTX, PCM_DRX,
285 PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MDIO,
286 WF0_DIG_RESETB, WF0_CBA_RESETB, WF0_XO_REQ, WF0_TOP_CLK,
287 WF0_TOP_DATA, WF0_HB1, WF0_HB2, WF0_HB3, WF0_HB4, WF0_HB0,
288 WF0_HB0_B, WF0_HB5, WF0_HB6, WF0_HB7, WF0_HB8, WF0_HB9,
289 WF0_HB10, WF1_DIG_RESETB, WF1_CBA_RESETB, WF1_XO_REQ,
290 WF1_TOP_CLK, WF1_TOP_DATA, WF1_HB1, WF1_HB2, WF1_HB3,
291 WF1_HB4, WF1_HB0, WF1_HB0_B, WF1_HB5, WF1_HB6, WF1_HB7,
300 description: normal pull up.
301 - enum: [100, 101, 102, 103]
303 PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
304 dt-bindings/pinctrl/mt65xx.h.
309 description: normal pull down.
310 - enum: [100, 101, 102, 103]
312 PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
313 dt-bindings/pinctrl/mt65xx.h.
325 input-schmitt-enable: true
327 input-schmitt-disable: true
330 enum: [2, 4, 6, 8, 10, 12, 14, 16]
332 mediatek,pull-up-adv:
334 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
335 Pull up settings for 2 pull resistors, R0 and R1. Valid arguments
336 are described as below:
337 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
338 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
339 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
340 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
341 $ref: /schemas/types.yaml#/definitions/uint32
344 mediatek,pull-down-adv:
346 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
347 Pull down settings for 2 pull resistors, R0 and R1. Valid arguments
348 are described as below:
349 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
350 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
351 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
352 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
353 $ref: /schemas/types.yaml#/definitions/uint32
359 additionalProperties: false
363 #include <dt-bindings/interrupt-controller/irq.h>
364 #include <dt-bindings/interrupt-controller/arm-gic.h>
365 #include <dt-bindings/pinctrl/mt65xx.h>
368 #address-cells = <2>;
370 pio: pinctrl@1001f000 {
371 compatible = "mediatek,mt7986a-pinctrl";
372 reg = <0 0x1001f000 0 0x1000>,
373 <0 0x11c30000 0 0x1000>,
374 <0 0x11c40000 0 0x1000>,
375 <0 0x11e20000 0 0x1000>,
376 <0 0x11e30000 0 0x1000>,
377 <0 0x11f00000 0 0x1000>,
378 <0 0x11f10000 0 0x1000>,
379 <0 0x1000b000 0 0x1000>;
380 reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
381 "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
384 gpio-ranges = <&pio 0 0 100>;
385 interrupt-controller;
386 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
387 interrupt-parent = <&gic>;
388 #interrupt-cells = <2>;
390 pcie_pins: pcie-pins {
393 groups = "pcie_clk", "pcie_wake", "pcie_pereset";
400 groups = "pwm0", "pwm1_0";
404 spi0_pins: spi0-pins {
407 groups = "spi0", "spi0_wp_hold";
411 uart1_pins: uart1-pins {
418 uart1_3_pins: uart1-3-pins {
421 groups = "uart1_3_rx_tx", "uart1_3_cts_rts";
425 uart2_pins: uart2-pins {
432 mmc0_pins_default: mmc0-pins {
438 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
439 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
440 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
442 drive-strength = <4>;
443 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
447 drive-strength = <6>;
448 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
452 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
456 drive-strength = <4>;
457 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */