1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx8ulp-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale IMX8ULP IOMUX Controller
10 - Jacky Bai <ping.bai@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
14 for common binding part and usage.
18 const: fsl,imx8ulp-iomuxc1
23 # Client device subnode's properties
28 Pinctrl node's client devices use subnodes for desired pin configuration.
29 Client device subnodes use below standard properties.
34 each entry consists of 5 integers and represents the mux and config
35 setting for one pin. The first 4 integers <mux_config_reg input_reg
36 mux_mode input_val> are specified using a PIN_FUNC_ID macro, which can
37 be found in <arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h>. The last
38 integer CONFIG is the pad setting value like pull-up on this pin. Please
39 refer to i.MX8ULP Reference Manual for detailed CONFIG settings.
40 $ref: /schemas/types.yaml#/definitions/uint32-matrix
44 "mux_config_reg" indicates the offset of mux register.
46 "input_reg" indicates the offset of select input register.
48 "mux_mode" indicates the mux value to be applied.
50 "input_val" indicates the select input value to be applied.
52 "pad_setting" indicates the pad configuration value to be applied.
57 additionalProperties: false
66 additionalProperties: false
69 # Pinmux controller node
71 iomuxc: pinctrl@298c0000 {
72 compatible = "fsl,imx8ulp-iomuxc1";
73 reg = <0x298c0000 0x10000>;
75 pinctrl_lpuart5: lpuart5grp {
77 <0x0138 0x08F0 0x4 0x3 0x3>,
78 <0x013C 0x08EC 0x4 0x3 0x3>;