1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/canaan,k210-fpioa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Canaan Kendryte K210 FPIOA
10 - Damien Le Moal <dlemoal@kernel.org>
13 The Canaan Kendryte K210 SoC Fully Programmable IO Array (FPIOA)
14 controller allows assigning any of 256 possible functions to any of
15 48 IO pins of the SoC. Pin function configuration is performed on
20 const: canaan,k210-fpioa
25 Address and length of the register set for the FPIOA controller.
29 - description: Controller reference clock source
30 - description: APB interface clock source
40 canaan,k210-sysctl-power:
41 $ref: /schemas/types.yaml#/definitions/phandle-array
44 - description: phandle of the K210 system controller node
45 - description: offset of its power domain control register
47 phandle of the K210 system controller node and offset of its
48 power domain control register.
53 $ref: /schemas/pinctrl/pinmux-node.yaml
55 FPIOA client devices use sub-nodes to define the desired pin
56 configuration. Client device sub-nodes use the pinux property
62 List of IO pins alternate functions. The values for each IO
63 pin is a combination of an IO pin number (0 to 47) with the
64 desired function for the IO pin. Functions are defined as
65 macros in include/dt-bindings/pinctrl/k210-fpioa.h.
66 The K210_FPIOA(IO pin, function) macro is provided to
67 facilitate the combination of IO pin numbers and functions.
72 additionalProperties: false
76 $ref: /schemas/pinctrl/pincfg-node.yaml
78 FPIOA client devices use sub-nodes to define the desired
79 configuration of pins. Client device sub-nodes use the
85 List of IO pins affected by the properties specified in this
86 subnode. IO pins are identified using the pin names "IO_xx".
87 Pin configuration nodes can also define the power domain to
88 be used for the SoC pin groups A0 (IO pins 0-5),
89 A1 (IO pins 6-11), A2 (IO pins 12-17), B0 (IO pins 18-23),
90 B1 (IO pins 24-29), B2 (IO pins 30-35), B3 (IO pins 30-35),
91 C0 (IO pins 36-41) and C1 (IO pins 42-47) using the
92 power-source property.
95 - pattern: "^(IO_([0-9]*))|(A[0-2])|(B[3-5])|(C[6-7])$"
96 - enum: [ IO_0, IO_1, IO_2, IO_3, IO_4, IO_5, IO_6, IO_7,
97 IO_8, IO_9, IO_10, IO_11, IO_12, IO_13, IO_14,
98 IO_15, IO_16, IO_17, IO_18, IO_19, IO_20, IO_21,
99 IO_22, IO_23, IO_24, IO_25, IO_26, IO_27, IO_28,
100 IO_29, IO_30, IO_31, IO_32, IO_33, IO_34, IO_35,
101 IO_36, IO_37, IO_38, IO_39, IO_40, IO_41, IO_42,
102 IO_43, IO_44, IO_45, IO_46, IO_47,
103 A0, A1, A2, B3, B4, B5, C6, C7 ]
112 drive-strength-microamp: true
118 input-schmitt-enable: true
120 input-schmitt-disable: true
122 input-polarity-invert:
125 Enable or disable pin input polarity inversion.
135 output-polarity-invert:
138 Enable or disable pin output polarity inversion.
144 additionalProperties: false
147 - $ref: pinctrl.yaml#
153 - canaan,k210-sysctl-power
155 additionalProperties: false
159 #include <dt-bindings/pinctrl/k210-fpioa.h>
160 #include <dt-bindings/clock/k210-clk.h>
161 #include <dt-bindings/reset/k210-rst.h>
163 fpioa: pinmux@502b0000 {
164 compatible = "canaan,k210-fpioa";
165 reg = <0x502b0000 0x100>;
166 clocks = <&sysclk K210_CLK_FPIOA>,
167 <&sysclk K210_CLK_APB0>;
168 clock-names = "ref", "pclk";
169 resets = <&sysrst K210_RST_FPIOA>;
170 canaan,k210-sysctl-power = <&sysctl 108>;
171 pinctrl-0 = <&jtag_pinctrl>;
172 pinctrl-names = "default";
174 jtag_pinctrl: jtag-pinmux {
175 pinmux = <K210_FPIOA(0, K210_PCF_JTAG_TCLK)>,
176 <K210_FPIOA(1, K210_PCF_JTAG_TDI)>,
177 <K210_FPIOA(2, K210_PCF_JTAG_TMS)>,
178 <K210_FPIOA(3, K210_PCF_JTAG_TDO)>;