1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/mtd/qcom,nandc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm NAND controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
26 - description: Core Clock
27 - description: Always ON Clock
37 $ref: raw-nand-chip.yaml
51 $ref: /schemas/types.yaml#/definitions/uint32-matrix
57 Boot partition use a different layout where the 4 bytes of spare
58 data are not protected by ECC. Use this to declare these special
59 partitions by defining first the offset and then the size.
61 It's in the form of <offset1 size1 offset2 size2 offset3 ...>
62 and should be declared in ascending order.
64 Refer to the ipq8064 example on how to use this special binding.
66 unevaluatedProperties: false
69 - $ref: nand-controller.yaml#
75 const: qcom,ipq806x-nand
80 - description: rxtx DMA channel
87 $ref: /schemas/types.yaml#/definitions/uint32
89 Must contain the ADM command type CRCI block instance number
90 specified for the NAND controller on the given platform
93 $ref: /schemas/types.yaml#/definitions/uint32
95 Must contain the ADM data type CRCI block instance number
96 specified for the NAND controller on the given platform
112 - description: tx DMA channel
113 - description: rx DMA channel
114 - description: cmd DMA channel
133 qcom,boot-partitions: true
138 qcom,boot-partitions: false
146 unevaluatedProperties: false
150 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
151 nand-controller@1ac00000 {
152 compatible = "qcom,ipq806x-nand";
153 reg = <0x1ac00000 0x800>;
155 clocks = <&gcc EBI2_CLK>,
157 clock-names = "core", "aon";
161 qcom,cmd-crci = <15>;
162 qcom,data-crci = <3>;
164 #address-cells = <1>;
170 nand-ecc-strength = <4>;
171 nand-bus-width = <8>;
173 qcom,boot-partitions = <0x0 0x58a0000>;
176 compatible = "fixed-partitions";
177 #address-cells = <1>;
187 reg = <0x58a0000 0x4000000>;
193 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
194 nand-controller@79b0000 {
195 compatible = "qcom,ipq4019-nand";
196 reg = <0x79b0000 0x1000>;
198 clocks = <&gcc GCC_QPIC_CLK>,
199 <&gcc GCC_QPIC_AHB_CLK>;
200 clock-names = "core", "aon";
205 dma-names = "tx", "rx", "cmd";
207 #address-cells = <1>;
212 nand-ecc-strength = <4>;
213 nand-bus-width = <8>;
216 compatible = "fixed-partitions";
217 #address-cells = <1>;
227 reg = <0x58a0000 0x4000000>;