1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Samsung Exynos SoC specific extensions to the Synopsys Designware Mobile
9 Storage Host Controller
12 - Jaehoon Chung <jh80.chung@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
19 - axis,artpec8-dw-mshc
20 - samsung,exynos4210-dw-mshc
21 - samsung,exynos4412-dw-mshc
22 - samsung,exynos5250-dw-mshc
23 - samsung,exynos5420-dw-mshc
24 - samsung,exynos5420-dw-mshc-smu
25 - samsung,exynos7-dw-mshc
26 - samsung,exynos7-dw-mshc-smu
29 - samsung,exynos5433-dw-mshc-smu
30 - samsung,exynos7885-dw-mshc-smu
31 - samsung,exynos850-dw-mshc-smu
32 - const: samsung,exynos7-dw-mshc-smu
43 Handle to "biu" and "ciu" clocks for the
44 bus interface unit clock and the card interface unit clock.
51 samsung,dw-mshc-ciu-div:
52 $ref: /schemas/types.yaml#/definitions/uint32
56 The divider value for the card interface unit (ciu) clock.
58 samsung,dw-mshc-ddr-timing:
59 $ref: /schemas/types.yaml#/definitions/uint32-array
61 - description: CIU clock phase shift value for tx mode
64 - description: CIU clock phase shift value for rx mode
68 The value of CUI clock phase shift value in transmit mode and CIU clock
69 phase shift value in receive mode for double data rate mode operation.
70 See also samsung,dw-mshc-hs400-timing property.
72 samsung,dw-mshc-hs400-timing:
73 $ref: /schemas/types.yaml#/definitions/uint32-array
75 - description: CIU clock phase shift value for tx mode
78 - description: CIU clock phase shift value for rx mode
82 The value of CIU TX and RX clock phase shift value for HS400 mode
84 Valid values for SDR and DDR CIU clock timing::
85 - valid value for tx phase shift and rx phase shift is 0 to 7.
86 - when CIU clock divider value is set to 3, all possible 8 phase shift
88 - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
89 phase shift clocks should be 0.
90 If missing, values from samsung,dw-mshc-ddr-timing property are used.
92 samsung,dw-mshc-sdr-timing:
93 $ref: /schemas/types.yaml#/definitions/uint32-array
95 - description: CIU clock phase shift value for tx mode
98 - description: CIU clock phase shift value for rx mode
102 The value of CIU clock phase shift value in transmit mode and CIU clock
103 phase shift value in receive mode for single data rate mode operation.
104 See also samsung,dw-mshc-hs400-timing property.
106 samsung,read-strobe-delay:
107 $ref: /schemas/types.yaml#/definitions/uint32
109 RCLK (Data strobe) delay to control HS400 mode (Latency value for delay
110 line in Read path). If missing, default from hardware is used.
118 - samsung,dw-mshc-ddr-timing
119 - samsung,dw-mshc-sdr-timing
122 - $ref: synopsys-dw-mshc-common.yaml#
128 - samsung,exynos5250-dw-mshc
129 - samsung,exynos5420-dw-mshc
130 - samsung,exynos7-dw-mshc
131 - samsung,exynos7-dw-mshc-smu
132 - axis,artpec8-dw-mshc
135 - samsung,dw-mshc-ciu-div
137 unevaluatedProperties: false
141 #include <dt-bindings/clock/exynos5420.h>
142 #include <dt-bindings/interrupt-controller/arm-gic.h>
145 compatible = "samsung,exynos5420-dw-mshc";
146 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
147 #address-cells = <1>;
149 reg = <0x12220000 0x1000>;
150 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
151 clock-names = "biu", "ciu";
153 card-detect-delay = <200>;
154 samsung,dw-mshc-ciu-div = <3>;
155 samsung,dw-mshc-sdr-timing = <0 4>;
156 samsung,dw-mshc-ddr-timing = <0 2>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
161 max-frequency = <200000000>;
162 vmmc-supply = <&ldo19_reg>;
163 vqmmc-supply = <&ldo13_reg>;