1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Xenon SDHCI Controller
10 This file documents differences between the core MMC properties described by
11 mmc-controller.yaml and the properties used by the Xenon implementation.
13 Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
14 Each SDHC is independent and owns independent resources, such as register
17 Each SDHC should have an independent device tree node.
20 - Ulf Hansson <ulf.hansson@linaro.org>
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
31 - marvell,armada-ap807-sdhci
33 - const: marvell,armada-ap806-sdhci
36 - const: marvell,armada-3700-sdhci
37 - const: marvell,sdhci-xenon
43 For "marvell,armada-3700-sdhci", two register areas. The first one
44 for Xenon IP register. The second one for the Armada 3700 SoC PHY PAD
45 Voltage Control register. Please follow the examples with compatible
46 "marvell,armada-3700-sdhci" in below.
47 Please also check property marvell,pad-type in below.
49 For other compatible strings, one register area for Xenon IP.
64 marvell,xenon-sdhc-id:
65 $ref: /schemas/types.yaml#/definitions/uint32
69 Indicate the corresponding bit index of current SDHC in SDHC System
70 Operation Control Register Bit[7:0]. Set/clear the corresponding bit to
71 enable/disable current SDHC.
73 marvell,xenon-phy-type:
74 $ref: /schemas/types.yaml#/definitions/string
79 Xenon support multiple types of PHYs. To select eMMC 5.1 PHY, set:
80 marvell,xenon-phy-type = "emmc 5.1 phy" eMMC 5.1 PHY is the default
81 choice if this property is not provided. To select eMMC 5.0 PHY, set:
82 marvell,xenon-phy-type = "emmc 5.0 phy"
84 All those types of PHYs can support eMMC, SD and SDIO. Please note that
85 this property only presents the type of PHY. It doesn't stand for the
86 entire SDHC type or property. For example, "emmc 5.1 phy" doesn't mean
87 that this Xenon SDHC only supports eMMC 5.1.
89 marvell,xenon-phy-znr:
90 $ref: /schemas/types.yaml#/definitions/uint32
96 Only available for eMMC PHY.
98 marvell,xenon-phy-zpr:
99 $ref: /schemas/types.yaml#/definitions/uint32
105 Only available for eMMC PHY.
107 marvell,xenon-phy-nr-success-tun:
108 $ref: /schemas/types.yaml#/definitions/uint32
113 Set the number of required consecutive successful sampling points
114 used to identify a valid sampling window, in tuning process.
116 marvell,xenon-phy-tun-step-divider:
117 $ref: /schemas/types.yaml#/definitions/uint32
120 Set the divider for calculating TUN_STEP.
122 marvell,xenon-phy-slow-mode:
125 If this property is selected, transfers will bypass PHY.
126 Only available when bus frequency lower than 55MHz in SDR mode.
127 Disabled by default. Please only try this property if timing issues
128 always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,
129 SD Default Speed and HS mode and eMMC legacy speed mode.
131 marvell,xenon-tun-count:
132 $ref: /schemas/types.yaml#/definitions/uint32
135 Xenon SDHC SoC usually doesn't provide re-tuning counter in
136 Capabilities Register 3 Bit[11:8].
137 This property provides the re-tuning counter.
140 - $ref: mmc-controller.yaml#
145 const: marvell,armada-3700-sdhci
151 - description: Xenon IP registers
152 - description: Armada 3700 SoC PHY PAD Voltage Control register
155 $ref: /schemas/types.yaml#/definitions/string
160 Type of Armada 3700 SoC PHY PAD Voltage Controller register.
161 If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning
162 and is switched to 1.8V when later in higher speed mode.
163 If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for
165 Please follow the examples with compatible
166 "marvell,armada-3700-sdhci" in below.
176 - marvell,armada-cp110-sdhci
177 - marvell,armada-ap807-sdhci
178 - marvell,armada-ap806-sdhci
197 unevaluatedProperties: false
202 #include <dt-bindings/interrupt-controller/arm-gic.h>
203 #include <dt-bindings/interrupt-controller/irq.h>
206 compatible = "marvell,armada-ap807-sdhci", "marvell,armada-ap806-sdhci";
207 reg = <0xaa0000 0x1000>;
208 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&emmc_clk 0>, <&axi_clk 0>;
210 clock-names = "core", "axi";
212 marvell,xenon-phy-slow-mode;
213 marvell,xenon-tun-count = <11>;
218 /* Vmmc and Vqmmc are both fixed */
223 #include <dt-bindings/interrupt-controller/arm-gic.h>
224 #include <dt-bindings/interrupt-controller/irq.h>
227 compatible = "marvell,armada-cp110-sdhci";
228 reg = <0xab0000 0x1000>;
229 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
230 vqmmc-supply = <&sd_vqmmc_regulator>;
231 vmmc-supply = <&sd_vmmc_regulator>;
232 clocks = <&sdclk 0>, <&axi_clk 0>;
233 clock-names = "core", "axi";
235 marvell,xenon-tun-count = <9>;
239 // For eMMC with compatible "marvell,armada-3700-sdhci":
240 #include <dt-bindings/interrupt-controller/arm-gic.h>
241 #include <dt-bindings/interrupt-controller/irq.h>
244 compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
245 reg = <0xaa0000 0x1000>,
247 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&emmcclk 0>;
249 clock-names = "core";
257 /* Vmmc and Vqmmc are both fixed */
259 marvell,pad-type = "fixed-1-8v";
263 // For SD/SDIO with compatible "marvell,armada-3700-sdhci":
264 #include <dt-bindings/interrupt-controller/arm-gic.h>
265 #include <dt-bindings/interrupt-controller/irq.h>
268 compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
269 reg = <0xab0000 0x1000>,
271 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
272 vqmmc-supply = <&sd_regulator>;
275 clock-names = "core";
278 marvell,pad-type = "sd";