1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare APB GPIO controller
10 Synopsys DesignWare GPIO controllers have a configurable number of ports,
11 each of which are intended to be represented as child nodes with the generic
12 GPIO-controller properties as described in this bindings file.
15 - Hoan Tran <hoan@os.amperecomputing.com>
16 - Serge Semin <fancer.lancer@gmail.com>
20 pattern: "^gpio@[0-9a-f]+$"
23 const: snps,dw-apb-gpio
37 - description: APB interface clock source
38 - description: DW GPIO debounce reference clock source
50 "^gpio-(port|controller)@[0-9a-f]+$":
54 const: snps,dw-apb-gpio-port
76 description: The number of GPIO pins exported by the port.
78 $ref: /schemas/types.yaml#/definitions/uint32
85 The interrupts to the parent controller raised when GPIOs generate
86 the interrupts. If the controller provides one combined interrupt
87 for all GPIOs, specify a single interrupt. If the controller provides
88 one interrupt for each GPIO, provide a list of interrupts that
89 correspond to each of the GPIO pins.
93 interrupt-controller: true
105 interrupt-controller: [ interrupts ]
107 additionalProperties: false
109 additionalProperties: false
120 compatible = "snps,dw-apb-gpio";
121 reg = <0x20000 0x1000>;
122 #address-cells = <1>;
126 compatible = "snps,dw-apb-gpio-port";
131 interrupt-controller;
132 #interrupt-cells = <2>;
133 interrupt-parent = <&vic1>;
138 compatible = "snps,dw-apb-gpio-port";