1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/gpio/gpio-stp-xway.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lantiq SoC Serial To Parallel (STP) GPIO controller
10 The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
11 peripheral controller used to drive external shift register cascades. At most
12 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
13 and Ethernet PHYs to drive some bytes of the cascade automatically.
16 - John Crispin <john@phrozen.org>
20 pattern: "^gpio@[0-9a-f]+$"
23 const: lantiq,gpio-stp-xway
32 The first cell is the pin number and the second cell is used to specify
38 The default value that we shall assume as already set on the
39 shift register cascade.
40 $ref: /schemas/types.yaml#/definitions/uint32
46 Set the 3 bit mask to select which of the 3 groups are enabled
47 in the shift register cascade.
48 $ref: /schemas/types.yaml#/definitions/uint32
54 The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit
55 property can enable this feature.
56 $ref: /schemas/types.yaml#/definitions/uint32
62 Use rising instead of falling edge for the shift register.
68 The gphy core can control 3 bits of the gpio cascade. In the xRX200 family
69 phy[1-2] are available, in xRX330 phy[1-3] and in XRX330 phy[1-4].
70 $ref: /schemas/types.yaml#/definitions/uint32
80 additionalProperties: false
85 compatible = "lantiq,gpio-stp-xway";
86 reg = <0xE100BB0 0x40>;
90 pinctrl-0 = <&stp_pins>;
91 pinctrl-names = "default";
93 lantiq,shadow = <0xffffff>;
94 lantiq,groups = <0x7>;