1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx firmware driver
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
13 firmware. ZynqMP has an interface to communicate with secure firmware.
14 Firmware driver provides an interface to firmware APIs. Interface APIs
15 can be used by any driver to communicate to PMUFW(Platform Management Unit).
16 These requests include clock management, pin control, device control,
17 power management service, FPGA service and other platform management
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
26 - description: For implementations complying for Versal.
27 const: xlnx,versal-firmware
31 The method of calling the PM-API firmware layer.
33 - "smc" : SMC #0, following the SMCCC
34 - "hvc" : HVC #0, following the SMCCC
36 $ref: /schemas/types.yaml#/definitions/string-array
41 "#power-domain-cells":
45 $ref: /schemas/fpga/xlnx,versal-fpga.yaml#
46 description: Compatible of the FPGA device.
50 $ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#
51 description: The ZynqMP AES-GCM hardened cryptographic accelerator is
52 used to encrypt or decrypt the data with provided key and initialization
57 $ref: /schemas/clock/xlnx,versal-clk.yaml#
58 description: The clock controller is a hardware block of Xilinx versal
59 clock tree. It reads required input clock frequencies from the devicetree
60 and acts as clock provider for all clock consumers of PS clocks.list of
61 clock specifiers which are external input clocks to the given clock
68 additionalProperties: false
72 #include <dt-bindings/power/xlnx-zynqmp-power.h>
74 zynqmp_firmware: zynqmp-firmware {
75 #power-domain-cells = <1>;
80 power-domains = <&zynqmp_firmware PD_SATA>;
84 compatible = "xlnx,versal-firmware";
87 versal_fpga: versal_fpga {
88 compatible = "xlnx,versal-fpga";
91 xlnx_aes: zynqmp-aes {
92 compatible = "xlnx,zynqmp-aes";
95 versal_clk: clock-controller {
97 compatible = "xlnx,versal-clk";
98 clocks = <&ref>, <&pl_alt_ref>;
99 clock-names = "ref", "pl_alt_ref";