1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/dsp/mediatek,mt8195-dsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek mt8195 DSP core
10 - YC Hung <yc.hung@mediatek.com>
13 Some boards from mt8195 contain a DSP core used for
14 advanced pre- and post- audio processing.
18 const: mediatek,mt8195-dsp
22 - description: Address and size of the DSP Cfg registers
23 - description: Address and size of the DSP SRAM
32 - description: mux for audio dsp clock
33 - description: 26M clock
34 - description: mux for audio dsp local bus
35 - description: default audio dsp local bus clock source
36 - description: clock gate for audio dsp clock
37 - description: mux for audio dsp access external bus
43 - const: audio_local_bus
44 - const: mainpll_d7_d2
45 - const: scp_adsp_audiodsp
53 - description: mailbox for receiving audio DSP requests.
54 - description: mailbox for transmitting requests to audio DSP.
63 - description: dma buffer between host and DSP.
64 - description: DSP system memory.
77 additionalProperties: false
81 #include <dt-bindings/interrupt-controller/arm-gic.h>
82 #include <dt-bindings/interrupt-controller/irq.h>
84 compatible = "mediatek,mt8195-dsp";
85 reg = <0x10803000 0x1000>,
87 reg-names = "cfg", "sram";
88 clocks = <&topckgen 10>, //CLK_TOP_ADSP
90 <&topckgen 107>, //CLK_TOP_AUDIO_LOCAL_BUS
91 <&topckgen 136>, //CLK_TOP_MAINPLL_D7_D2
92 <&scp_adsp 0>, //CLK_SCP_ADSP_AUDIODSP
93 <&topckgen 34>; //CLK_TOP_AUDIO_H
94 clock-names = "adsp_sel",
100 memory-region = <&adsp_dma_mem_reserved>,
101 <&adsp_mem_reserved>;
102 power-domains = <&spm 6>; //MT8195_POWER_DOMAIN_ADSP
103 mbox-names = "rx", "tx";
104 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;