1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/dma/qcom,adm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm ADM DMA Controller
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
14 QCOM ADM DMA controller provides DMA capabilities for
15 peripheral buses such as NAND and SPI.
32 - description: phandle to the core clock
33 - description: phandle to the iface clock
42 - description: phandle to the clk reset
43 - description: phandle to the pbus reset
44 - description: phandle to the c0 reset
45 - description: phandle to the c1 reset
46 - description: phandle to the c2 reset
57 $ref: /schemas/types.yaml#/definitions/uint32
58 description: indicates the security domain identifier used in the secure world.
73 additionalProperties: false
77 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
78 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
80 adm_dma: dma-controller@18300000 {
81 compatible = "qcom,adm";
82 reg = <0x18300000 0x100000>;
83 interrupts = <0 170 0>;
86 clocks = <&gcc ADM0_CLK>,
88 clock-names = "core", "iface";
90 resets = <&gcc ADM0_RESET>,
91 <&gcc ADM0_PBUS_RESET>,
95 reset-names = "clk", "pbus", "c0", "c1", "c2";