1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/dma/ingenic,dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs DMA Controller
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: dma-controller.yaml#
26 - ingenic,jz4760b-bdma
27 - ingenic,jz4760b-mdma
33 - const: ingenic,jz4770-bdma
34 - const: ingenic,jz4760b-bdma
38 - description: Channel-specific registers
39 - description: System control registers
50 DMA clients must use the format described in dma.txt, giving a phandle
51 to the DMA controller plus the following integer cells:
53 - Request type: The DMA request type specifies the device endpoint that
54 will be the source or destination of the DMA transfer.
55 If "#dma-cells" is 2, the request type is a single cell, and the
56 direction will be unidirectional (either RX or TX but not both).
57 If "#dma-cells" is 3, the request type has two cells; the first
58 one corresponds to the host to device direction (TX), the second one
59 corresponds to the device to host direction (RX). The DMA channel is
62 - Channel: If set to 0xffffffff, any available channel will be allocated
63 for the client. Otherwise, the exact channel specified will be used.
64 The channel should be reserved on the DMA controller using the
65 ingenic,reserved-channels property.
67 ingenic,reserved-channels:
68 $ref: /schemas/types.yaml#/definitions/uint32
70 Bitmask of channels to reserve for devices that need a specific
71 channel. These channels will only be assigned when explicitly
72 requested by a client. The primary use for this is channels 0 and
73 1, which can be configured to have special behaviour for NAND/BCH
74 when using programmable firmware.
82 unevaluatedProperties: false
86 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
87 dma: dma-controller@13420000 {
88 compatible = "ingenic,jz4780-dma";
89 reg = <0x13420000 0x400>, <0x13421000 0x40>;
91 interrupt-parent = <&intc>;
94 clocks = <&cgu JZ4780_CLK_PDMA>;
98 ingenic,reserved-channels = <0x3>;